Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

Read this for an introduction to the processor and descriptions of the major features.

Chapter 2 Functional Description

Read this for a description of the functionality of the processor.

Chapter 3 Programmers Model

Read this for a description of the programmers model.

Chapter 4 System Control

Read this for a description of the System registers and programming information.

Chapter 5 Memory Management Unit

Read this for a description of the Memory Management Unit (MMU) and the address translation process.

Chapter 6 Level 1 Memory System

Read this for a description of the Level 1 (L1) memory system that consists of separate instruction and data caches.

Chapter 7 Level 2 Memory System

Read this for a description of the Level 2 (L2) memory system.

Chapter 8 Generic Interrupt Controller CPU Interface

Read this for a description of the Generic Interrupt Controller (GIC) CPU interface.

Chapter 9 Generic Timer

Read this for a description of the Generic Timer.

Chapter 10 Debug

Read this for a description of the processor support for debug.

Chapter 11 Performance Monitor Unit

Read this for a description of the Performance Monitor Unit (PMU).

Chapter 12 Cross Trigger

Read this for a description of the cross trigger interfaces.

Chapter 13 Embedded Trace Macrocell

Read this for a description of the processor support for instruction trace.

Chapter 14 Advanced SIMD and Floating-point

Read this for a description of the Advanced SIMD and Floating-Point (FP) unit.

Appendix A Signal Descriptions

Read this for a description of the signals in the processor.

Appendix B AArch32 UNPREDICTABLE Behaviors

Read this for a description of the unpredictable behaviors that the processor implements.

Appendix C Revisions

Read this for a description of the technical changes between released issues of this book.

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