4.3.64 RAM Index operation

The RAMINDEX characteristics are:
Purpose
Read the instruction side L1 array contents into the IL1DATAn register or read the data side L1 or L2 array contents into the DL1DATAn register.
Usage constraints
The accessibility to the RAMINDEX by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- WO WO WO WO WO
Configurations
The RAMINDEX operates in the Secure and Non-secure states.
The RAMINDEX command takes one argument or source register. You must write an ARM core register with the bit pattern described in the following figure for each RAM listed in the following table.
A 32-bit register in AArch64 state.
Attributes
See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the RAMINDEX bit assignments.
Figure 4-56 RAMINDEX bit assignments
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The following table shows the RAMINDEX bit assignments.

Table 4-75 RAMINDEX bit assignments

Bits Name Function
[31:24] RAMID
RAM identifier. This field indicates which RAM is being accessed. The possible values are a:
0x00
L1-I Tag RAM, see L1-I Tag RAM.
0x01
L1-I Data RAM, see L1-I Data RAM.
0x02
L1-I BTB RAM, see L1-I BTB RAM.
0x03
L1-I GHB RAM, see L1-I GHB RAM.
0x04
L1-I TLB array, see L1-I TLB array.
0x05
L1-I indirect predictor RAM, see L1-I indirect predictor RAM.
0x08
L1-D Tag RAM, see L1-D Tag RAM.
0x09
L1-D Data RAM, see L1-D Data RAM.
0x0A
L1-D TLB array, see L1-D TLB array.
0x10
L2 Tag RAM, see L2 Tag RAM.
0x11
L2 Data RAM, see L2 Data RAM.
0x12
L2 Snoop Tag RAM, see L2 Snoop Tag RAM.
0x13
L2 Data ECC RAM, see L2 Data ECC RAM.
0x14
L2 Dirty RAM, see L2 Dirty RAM.
0x18
L2 TLB RAM, see L2 TLB RAM.
All other values are reserved.
[23:22] - Reserved, RES0.
[21:18] Way Indicates the way of the RAM that is being accessed.
[17:0] Index Indicates the index address of the RAM that is being accessed.

Note

  • Executing a RAMINDEX operation with a reserved value of RAMID, Way, or Index results in the corruption of the IL1DATAn or DL1DATAn register contents.
  • In Non-secure EL1 and EL2, the RAMINDEX operation returns the contents of the RAM only if the entry is marked valid and Non-secure. Entries that are marked invalid or Secure update the IL1DATAn or DL1DATAn registers with 0x0 values.
  • In Secure EL1 or EL3, the RAMINDEX operation returns the contents of the RAM, regardless of whether the entry is marked valid or invalid, and Secure or Non-secure.
  • When the RAMID field is set to L1-I BTB RAM in Non-secure EL1 and EL2, the RAMINDEX operation always returns zero.
  • The L1-I, L1-D, L2 TLB, and L2 Snoop Tag RAMs can only be accessed by the processor where the RAM resides or that owns the RAM.
  • The L2 Tag, Data, and Dirty RAMs can be accessed by any processor.

L1-I Tag RAM

The following figure shows the RAMINDEX register bit assignments for accessing L1-I Tag RAM.
Figure 4-57 RAMINDEX bit assignments for L1-I Tag RAM
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The RAMINDEX address bits for accessing L1-I Tag RAM are:
Way[1:0]
Way select.

Note

The instruction cache is 3-way set-associative. Setting the way field to a value of 3, reads way 2 of the cache.
VA[13:7]
Row select.
VA[6]
Bank select.
The data returned from accessing L1-I Tag RAM are:
ILDATA1[1]
Valid bit.
ILDATA1[0]
Non-secure identifier for the physical address.
ILDATA0
Physical address tag [43:12].

L1-I Data RAM

The following figure shows the RAMINDEX bit assignments for accessing L1-I Data RAM.
Figure 4-58 RAMINDEX bit assignments for L1-I Data RAM
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The RAMINDEX address bits for accessing L1-I Data RAM are:
Way[1:0]
Way select.

Note

The instruction cache is 3-way set-associative. Setting the Way field to 3, reads way 2 of the cache.
VA[13:6]
Set select.
VA[5:4]
Bank select.
VA[3]
Upper or lower doubleword within the quadword.
The data returned from accessing L1-I Data RAM are:
ILDATA1[31:0]
Data word 1.
ILDATA0[31:0]
Data word 0.

L1-I BTB RAM

The following figure shows the RAMINDEX bit assignments for accessing L1-I BTB RAM.
Figure 4-59 RAMINDEX bit assignments for L1-I BTB RAM
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The RAMINDEX address bits for accessing L1-I BTB RAM are:
VA[14:6]
Row select.
VA[5:4]
Bank select.
ARM does not disclose the format of the returned data.

L1-I GHB RAM

The following figure shows the RAMINDEX bit assignments for accessing L1-I GHB RAM.
Figure 4-60 RAMINDEX bit assignments for L1-I GHB RAM
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The RAMINDEX address bits for accessing L1-I GHB RAM are:
Index[13:5]
Row select.
Index[4]
Bank select.
ARM does not disclose the format of the returned data.

L1-I TLB array

The following figure shows the RAMINDEX bit assignments for accessing L1-I TLB array.
Figure 4-61 RAMINDEX bit assignments for L1-I TLB array
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The RAMINDEX address bits for accessing L1-I TLB array are:
TLB entry
Selects one of the 48 entries.
The data returned from accessing L1-I TLB array are:
ILDATA3[27]
Valid bit.
ILDATA3[26:25]
Shareability attribute:
0b00
Non-Shareable.
0b01
Reserved.
0b10
Outer Shareable.
0b11
Inner Shareable.
ILDATA3[15:14]
VA memory space ID:
0b00
Secure EL1.
0b01
EL3, AArch64 only.
0b10
Non-secure EL1.
0b11
Non-secure EL2.
ILDATA3[13:6]
Virtual Machine ID (VMID).
{ILDATA3[5:0], ILDATA2[31:22]}
Address Space ID (ASID).
ILDATA2[21:14]
Memory Attribute Indirection Register.
ILDATA2[11:10]
Page size:
0b00
4KB.
0b01
64KB.
0b10
1MB.
0b11
Reserved.
ILDATA2[9:6]
Domain ID.
ILDATA2[5]
Non-secure identifier for the physical address.
{ILDATA2[4:0], ILDATA1[31:5]}
Physical address [43:12].
{ILDATA1[4:0], ILDATA0[31:0]}
Virtual address [48:12].

L1-I indirect predictor RAM

The following figure shows the RAMINDEX bit assignments for accessing L1-I indirect predictor RAM.
Figure 4-62 RAMINDEX bit assignments for L1-I indirect predictor RAM
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The RAMINDEX address bits for accessing L1-I indirect predictor RAM are:
Way
Way select.
Index[7:0]
Indirect predictor entry.
ARM does not disclose the format of the returned data.

L1-D Tag RAM

The following figure shows the RAMINDEX bit assignments for accessing L1-D Tag RAM.
Figure 4-63 RAMINDEX bit assignments for L1-D Tag RAM
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The RAMINDEX address bits for accessing L1-D Tag RAM are:
WayWay select.
PA[13:8]Row select.
PA[7:6]Bank select.
The data returned from accessing L1-D Tag RAM are:
DL1DATA1[1:0]
MESI state:
0b00Invalid.
0b01Exclusive.
0b10Shared.
0b11Modified.
DL1DATA0[30]Non-secure identifier for the physical address.
DL1DATA0[29:0]Physical address tag [43:14].

L1-D Data RAM

The following figure shows the RAMINDEX bit assignments for accessing L1-D Data RAM.

Figure 4-64 RAMINDEX bit assignments for L1-D Data RAM
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The RAMINDEX address bits for accessing L1-D Data RAM are:
WayWay select.
PA[13:6]Set select.
PA[5:4]Bank select.
PA[3]Upper or lower doubleword within the quadword.
The data returned from accessing L1-D Data RAM are:
DL1DATA1[31:0]Data word 1.
DL1DATA0[31:0]Data word 0.

L1-D TLB array

The following figure shows the RAMINDEX bit assignments for accessing L1-D TLB array.
Figure 4-65 RAMINDEX bit assignments for L1-D TLB array
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The RAMINDEX address bits for accessing L1-D TLB array are:
TLB entry
Selects one of the 32 entries.
The data returned from accessing L1-D TLB array are:
DL1DATA3[12]
Valid bit.
DL1DATA3[11:10]
VA memory space ID:
0b00
Secure EL1.
0b01
EL3, AArch64 only.
0b10
Non-secure EL1.
0b11
Non-secure EL2.
DL1DATA3[1:0]
Shareability attribute:
0b00
Non-Shareable.
0b01
Reserved.
0b10
Outer Shareable.
0b11
Inner Shareable.
DL1DATA2[31:24]
Memory Attribute Indirection Register.
DL1DATA2[23:22]
Page size:
0b00
4KB.
0b01
64KB.
0b10
1MB.
0b11
Reserved.
DL1DATA2[21:18]
Domain ID.
DL1DATA2[5]
Non-secure identifier for the physical address.
{DL1DATA2[4:0], DL1DATA1[31:5]}
Physical address [43:12].
{DL1DATA1[4:0], DL1DATA0[31:0]}
Virtual address [48:12].

L2 Tag RAM

The following figure shows the RAMINDEX bit assignments for accessing L2 Tag RAM.
Figure 4-66 RAMINDEX bit assignments for L2 Tag RAM
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The RAMINDEX address bits for accessing L2 Tag RAM are:
Way[3:0]
Way select.
PA[16:7]
Row select.
PA[6]
Tag bank select.
The data returned from accessing L2 Tag RAM are:
DL1DATA0[31]
Non-secure identifier for the physical address.
DL1DATA0[30:2]
Physical address tag [43:15].
DL1DATA0[1:0]
MOESI state:
0b00
Invalid.
0b01
Exclusive or Modified.
0b10
Reserved.
0b11
Shared or Owned.

Note

The Dirty bit in the L2 Dirty RAM must be used to differentiate between the Exclusive, Modified, Shared, and Owned states.

L2 Data RAM

The following figure shows the RAMINDEX bit assignments for accessing L2 Data RAM.
Figure 4-67 RAMINDEX bit assignments for L2 Data RAM
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The RAMINDEX address bits for accessing L2 Data RAM are:
Way[3:0]
Way select.
PA[16:7]
Row select.
PA[6]
Tag bank select.
PA[5:4]
Data bank select.
The data returned from accessing L2 Data RAM are:
DL1DATA3
Data[127:96].
DL1DATA2
Data[95:64].
DL1DATA1
Data[63:32].
DL1DATA0
Data[31:0].

L2 Snoop Tag RAM

The following figure shows the RAMINDEX bit assignments for accessing L2 Snoop Tag RAM.
Figure 4-68 RAMINDEX bit assignments for L2 Snoop Tag RAM
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The RAMINDEX address bits for accessing L2 Snoop Tag RAM are:
CPUID[1:0]
Processor ID of the executing processor that has access to the L2 Snoop Tag RAM.
Way
Way select.
PA[13:7]
Row select.
PA[6]
Bank select.
The data returned from accessing L2 Snoop Tag RAM are:
DL1DATA1[0]
Non-secure identifier for the physical address.
DL1DATA0[31:2]
Physical address tag [43:14].
DL1DATA0[1:0]
MESI state:
0b00
Invalid.
0b01
Exclusive or Modified.
0b10
Reserved.
0b11
Shared.

L2 Data ECC RAM

The following figure shows the RAMINDEX bit assignments for accessing L2 Data ECC RAM.
Figure 4-69 RAMINDEX bit assignments for L2 Data ECC RAM
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The RAMINDEX address bits for accessing L2 Data ECC RAM are:
Way[3:0]
Way select.
PA[16:7]
Row select.
PA[6]
Tag bank select.
PA[5:4]
Data bank select.
ARM does not disclose the format of the returned data.

L2 Dirty RAM

The following figure shows the RAMINDEX bit assignments for accessing L2 Dirty RAM.
Figure 4-70 RAMINDEX bit assignments for L2 Dirty RAM
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The RAMINDEX address bits for accessing L2 Dirty RAM are:
Way[3:0]
Way select.
PA[16:7]
Row select.
PA[6]
Tag bank select.
The data returned from accessing L2 Dirty RAM are:
DL1DATA0[7]
Outer Shareable page attribute.
DL1DATA0[6]
Read Allocate page attribute.
DL1DATA0[5]
Write Allocate page attribute.
DL1DATA0[4]
Inner Shareable page attribute.
DL1DATA0[0]
Dirty bit indicator.

L2 TLB RAM

The following figure shows the RAMINDEX bit assignments for accessing L2 TLB RAM.
Figure 4-71 RAMINDEX bit assignments for L2 TLB RAM
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The RAMINDEX address bits for accessing L2 TLB RAM are:
Way
Way select.
TLB entry
Selects one of the 256 entries in each way.
The data returned from accessing L2 TLB RAM are:
DL1DATA3[31]
Valid bit for EL3 AArch64 only.
DL1DATA3[30]
Valid bit for EL2.
DL1DATA3[29]
Valid bit for Secure EL1.
DL1DATA3[28]
Valid bit for Non-secure EL1.

Note

Only a single bit in DLDATA3[31:28] is set to 1.
DL1DATA3[27:20]
VMID.
DL1DATA3[19:4]
ASID.
{DL1DATA3[3:0], DL1DATA2[31:6]}
Virtual address [48:19].
DL1DATA2[5]
Non-secure identifier for the physical address.
{DL1DATA2[4:0], DL1DATA1[31:5]}
Physical address [43:12].
{DL1DATA1[1:0], DL1DATA0[31]}
Fully resolved page size:
0b000
4KB.
0b001
64KB.
0b010
1MB.
0b011
2MB.
0b100
16MB.
0b101
1GB.
DL1DATA0[13:10]
Domain ID.
DL1DATA0[9:8]
Shareability attribute:
0b00
Non-Shareable.
0b01
Reserved.
0b10
Outer Shareable.
0b11
Inner Shareable.
DL1DATA0[7:0]
Memory Attribute Indirection Register.
For example, to read an entry in the instruction side TLB in AArch64 state:
LDR X0, =0x0000000001000D80
SYS #0, c15, c4, #0, X0
DSB SY
ISB
MRS X1, S3_0_c15_c0_0 ; Move ILData0 register to X1
MRS X2, S3_0_c15_c0_1 ; Move ILData1 register to X2
MRS X3, S3_0_c15_c0_2 ; Move ILData2 register to X3
MRS X4, S3_0_c15_c0_3 ; Move ILData3 register to X4
To complete the RAMINDEX operation in AArch64 state, use the following instruction:
SYS #0, c15, c4, #0, X0 ; Execute RAMINDEX operation
For example, to read one entry in the instruction side L1 data array in AArch32 state:
LDR R0, =0x01000D80;
MCR p15, 0, R0, c15, c4, 0; Read I-L1 TLB data into IL1DATA0-2
DSB
ISB
MRC p15, 0, R1, c15, c0, 0; Move IL1DATA0 Register to R1
MRC p15, 0, R2, c15, c0, 1; Move IL1DATA1 Register to R2
MRC p15, 0, R3, c15, c0, 2; Move IL1DATA2 Register to R3
To complete the RAMINDEX operation in AArch32 state, use the following instruction:
MCR p15, 0, <Rt>, c15, c4, 0; Execute RAMINDEX operation
a All other values reserved.
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