2.4.2 Power domains

The processor supports the following power domains:

  • Each core in the device.
  • The L2 cache and Snoop Tag RAMs.
  • A domain for:
    • The L2 control.
    • The GIC CPU interface.
    • The Generic Timer logic.
  • The PCLKDBG domain for:
    • The Debug APB interface.
    • The CTI logic.
    • The CTM logic.


  • The design does not support a separate power domain for the L1 cache and branch prediction RAMs within the core. It does not support L1 cache retention when the core is powered down.
  • For L2 RAMs dynamic retention, the L2 Data, Dirty, Tag, Inclusion PF, and Snoop Tag RAMs are retained. For L2 cache Dormant mode, the L2 Data, Dirty, Tag, and Inclusion PF RAMs are retained.
  • The L2 Inclusion PF RAM is available only in r1p0 and later revisions.
The following figure shows the supported power domains in the processor and the placeholders where you can insert clamps for a core.
Figure 2-17 Power domains
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