4.2.1 AArch64 identification registers

The following table shows the identification registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the table.

Table 4-1 AArch64 identification registers

Name Type Reset Width Description
MIDR_EL1 RO 411FD072 32 4.3.1 Main ID Register, EL1
MPIDR_EL1 RO 0x80000003a 64 4.3.2 Multiprocessor Affinity Register, EL1
REVIDR_EL1 RO 0x00000000 32 4.3.3 Revision ID Register, EL1
ID_PFR0_EL1 RO 0x00000131 32 4.3.4 AArch32 Processor Feature Register 0, EL1
ID_PFR1_EL1 RO 0x00011011b 32 4.3.5 AArch32 Processor Feature Register 1, EL1
ID_DFR0_EL1 RO 0x03010066 32
ID_AFR0_EL1 RO 0x00000000 32 4.3.7 AArch32 Auxiliary Feature Register 0, EL1
ID_MMFR0_EL1 RO 0x10101105 32 4.3.8 AArch32 Memory Model Feature Register 0, EL1
ID_MMFR1_EL1 RO 0x40000000 32 4.3.9 AArch32 Memory Model Feature Register 1, EL1
ID_MMFR2_EL1 RO 0x01260000 32 4.3.10 AArch32 Memory Model Feature Register 2, EL1
ID_MMFR3_EL1 RO 0x02102211 32 4.3.11 AArch32 Memory Model Feature Register 3, EL1
ID_ISAR0_EL1 RO 0x02101110 32 4.3.12 AArch32 Instruction Set Attribute Register 0, EL1
ID_ISAR1_EL1 RO 0x13112111 32 4.3.13 AArch32 Instruction Set Attribute Register 1, EL1
ID_ISAR2_EL1 RO 0x21232042 32 4.3.14 AArch32 Instruction Set Attribute Register 2, EL1
ID_ISAR3_EL1 RO 0x01112131 32 4.3.15 AArch32 Instruction Set Attribute Register 3, EL1
ID_ISAR4_EL1 RO 0x00011142 32 4.3.16 AArch32 Instruction Set Attribute Register 4, EL1
ID_ISAR5_EL1 RO 0x00010001c 32 4.3.17 AArch32 Instruction Set Attribute Register 5, EL1
ID_AA64PFR0_EL1 RO 0x00002222 64 4.3.18 AArch64 Processor Feature Register 0, EL1
ID_AA64DFR0_EL1 RO 0x10305106 64 4.3.19 AArch64 Debug Feature Register 0, EL1
ID_AA64ISAR0_EL1 RO 0x00010000d 64 4.3.20 AArch64 Instruction Set Attribute Register 0, EL1
ID_AA64MMFR0_EL1 RO 0x00001124 64 4.3.21 AArch64 Memory Model Feature Register 0, EL1
CCSIDR_EL1 RO UNK 32 4.3.22 Cache Size ID Register, EL1
CLIDR_EL1 RO 0x0A200023 32 4.3.23 Cache Level ID Register, EL1
AIDR_EL1 - 0x00000000 32 4.3.24 Auxiliary ID Register, EL1
CSSELR_EL1 RW UNK 32 4.3.25 Cache Size Selection Register, EL1
CTR_EL0 RO 0x8444C004 32 4.3.26 Cache Type Register, EL0
DCZID_EL0 RO 0x00000004 32 4.3.27 Data Cache Zero ID, EL0
VPIDR_EL2 RW -e 32 4.3.28 Virtualization Processor ID Register, EL2
VMPIDR_EL2 RO -f 64 4.3.2 Multiprocessor Affinity Register, EL1
a The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the processor implements. The value shown is for a four-core implementation, with CLUSTERIDAFF1 and CLUSTERIDAFF2 set to zero.
b The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.
c The reset value is 0x00011121 if the Cryptography engine is implemented.
d The reset value is 0x00011120 if the Cryptography engine is implemented.
e The reset value is the value of the Main ID Register.
f The reset value is the value of the Multiprocessor Affinity Register.
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