4.3.1 Main ID Register, EL1

The MIDR_EL1 characteristics are:
Purpose
Provides identification information for the processor, including an implementer code for the device and a device ID number.
Usage constraints
The accessibility to the MIDR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
The external debug accessibility to the MIDR by condition code is:
Off DLK OSLK EDAD SLK Default
RO RO RO RO RO RO
Table 10-1 External register access conditions describes the condition codes.
Configurations
The MIDR_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 MIDR register.
  • Architecturally mapped to external MIDR register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the MIDR_EL1 bit assignments.
Figure 4-1 MIDR_EL1 bit assignments
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The following table shows the MIDR_EL1 bit assignments.

Table 4-16 MIDR_EL1 bit assignments

Bits Name Function
[31:24] Implementer
Indicates the implementer code. This value is:
0x41
ARM Limited.
[23:20] Variant
Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status. This value is:
1
Major revision number.
[19:16] Architecture
Indicates the architecture code. This value is:
0xF
Defined by CPUID scheme.
[15:4] Primary part number
Indicates the primary part number. This value is:
0xD07
Cortex-A57 processor.
[3:0] Revision
Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status. This value is:
2
Minor revision number.
To access the MIDR_EL1 in AArch64 state, read the register with:
MRS <Xt>, MIDR_EL1; Read Main ID Register
To access the MIDR in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c0, 0; Read Main ID Register
The MIDR can be accessed through the memory-mapped interface and the external debug interface, offset 0xD00.
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