4.3.3 Revision ID Register, EL1

The REVIDR_EL1 characteristics are:
Provides implementation-specific minor revision information that can only be interpreted in conjunction with the MIDR_EL1.
Usage constraints
The accessibility to the REVIDR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The REVIDR_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 REVIDR register.
The REVIDR_EL1 is a 32-bit register.
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the REVIDR_EL1 bit assignments.
Figure 4-3 REVIDR_EL1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the REVIDR_EL1 bit assignments.

Table 4-18 REVIDR_EL1 bit assignments

Bits Name Function
[31:0] ID number Implementation-specific revision information. The reset value is determined by the specific Cortex-A57 processor implementation.
To access the REVIDR_EL1 in AArch64 state, read the register with:
MRS <Xt>, REVIDR_EL1; Read Revision ID Register
To access the REVIDR in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c0, 6; Read Revision ID Register
Non-ConfidentialPDF file icon PDF versionARM DDI0488F
Copyright © 2013, 2014 ARM. All rights reserved.