4.3.6 AArch32 Debug Feature Register 0, EL1

The ID_DFR0_EL1 characteristics are:
Purpose
Provides top-level information about the debug system in AArch32 state.
Usage constraints
The ID_DFR0_EL1 must be interpreted with the MIDR_EL1.
The accessibility to the ID_DFR0_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The ID_DFR0_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 ID_DFR0 register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_DFR0_EL1 bit assignments.
Figure 4-6 ID_DFR0_EL1 bit assignments
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The following table shows the ID_DFR0_EL1 bit assignments.

Table 4-21 ID_DFR0_EL1 bit assignments

Bits Name Function
[31:28] - Reserved, RES0.
[27:24] PerfMon
Indicates support for coprocessor-based ARM Performance Monitors Extension. This value is:
0x3
Processor supports Performance Monitors Extension, PMUv3 System registers.
[23:20] MProfDbg
Indicates support for memory-mapped debug model for M-profile processors. This value is:
0x0
Processor does not support M-profile Debug architecture, with memory-mapped access.
[19:16] MMapTrc
Indicates support for memory-mapped trace model. This value is:
0x1
Processor supports ARM trace architecture, with memory-mapped access.
[15:12] CopTrc
Indicates support for coprocessor-based trace model. This value is:
0x0
Processor does not support ARM trace architecture, with CP14 access.
[11:8] MMapDbg
Indicates support for memory-mapped debug model. This value is:
0x0
Processor does not support the memory-mapped debug model.
[7:4] CopSDbg
Indicates support for coprocessor-based Secure debug model. This value is:
0x6
Processor supports v8-A Debug architecture, with CP14 access.
[3:0] CopDbg
Indicates support for coprocessor-based debug model. This value is:
0x6
Processor supports v8-A Debug architecture, with CP14 access.
To access the ID_DFR0_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_DFR0_EL1; Read AArch32 Debug Feature Register 0
To access the ID_DFR0 in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c1, 2; Read AArch32 Debug Feature Register 0
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