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4.3.16 AArch32 Instruction Set Attribute Register 4, EL1

The ID_ISAR4_EL1 characteristics are:
Purpose
Provides information about the instruction set that the processor supports in AArch32.
Usage constraints
The ID_ISAR4_EL1 must be interpreted with:
  • ID_ISAR0_EL1.
  • ID_ISAR1_EL1.
  • ID_ISAR2_EL1.
  • ID_ISAR3_EL1.
  • ID_ISAR5_EL1.
The accessibility to the ID_ISAR4_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The ID_ISAR4_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 ID_ISAR4 register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_ISAR4_EL1 bit assignments.
Figure 4-15 ID_ISAR4_EL1 bit assignments
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The following table shows the ID_ISAR4_EL1 bit assignments.

Table 4-30 ID_ISAR4_EL1 bit assignments

Bits Name Function
[31:28] SWP_frac Returns 0x0 to indicate that SWP or SWPB instructions are not implemented.
[27:24] PSR_M Returns 0x0 to indicate that M-profile instructions, that modify the PSRs, are not implemented.
[23:20] SynchPrim_frac
This field is used with the SynchPrim field of ID_ISAR3_EL1 to indicate the supported Synchronization Primitive instructions. This value is:
0x0
Processor supports:
  • LDREX and STREX instructions.
  • CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.
  • LDREXD and STREXD instructions.
[19:16] Barrier Returns 0x1 to indicate the processor implements the DMB, DSB, and ISB barrier instructions in the A32 and T32 instruction sets.
[15:12] SMCs Returns 0x1 to indicate the processor implements the SMC instruction.
[11:8] Writeback Returns 0x1 to indicate the processor supports all writeback addressing modes defined in ARMv8 architecture.
[7:4] WithShifts
Returns 0x4 to indicate the processor supports the following instructions with shifts:
  • Shifts of loads and stores over the range LSL 0-3.
  • Constant shift options, both on load/store and other instructions.
  • Register-controlled shift options.
See the ARM® Architecture Reference Manual ARMv8 for more information.
[3:0] Unpriv
Returns 0x2 to indicate the processor implements the following unprivileged instructions:
  • LDRBT, LDRT, STRBT, and STRT.
  • LDRHT, LDRSBT, LDRSHT, and STRHT.
To access the ID_ISAR4_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_ISAR4_EL1; Read AArch32 Instruction Set Attribute Register 4
To access the ID_ISAR4 in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c2, 4; Read AArch32 Instruction Set Attribute Register 4
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