4.3.28 Virtualization Processor ID Register, EL2

The VPIDR_EL2 characteristics are:
Purpose
Holds the value of the Virtualization Processor ID. A Non-secure read of the MIDR from EL1 returns the value of this register.
Usage constraints
The accessibility to the VPIDR_EL2 in AArch64 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW
The accessibility to the VPIDR in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW -
Configurations
The VPIDR_EL2 is:
  • A Banked EL2 register.
  • Architecturally mapped to the AArch32 VPIDR register.
Attributes
See the register summary in Table 4-13 AArch64 virtualization registers.
The following figure shows the VPIDR_EL2 bit assignments.
Figure 4-26 VPIDR_EL2 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the VPIDR_EL2 bit assignments.

Table 4-42 VPIDR_EL2 bit assignments

Bits Name Function
[31:0] VPIDR MIDR value returned by Non-secure EL1 reads of the MIDR. For information on the subdivision of this value, see 4.3.1 Main ID Register, EL1.
To access the VPIDR_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, VPIDR_EL1; Read Virtualization Processor ID Register
MSR VPIDR_EL1, <Xt>; Write Virtualization Processor ID Register
To access the VPIDR, read or write the CP15 register with:
MRC p15, 4, <Rt>, c0, c0, 0; Read Virtualization Processor ID Register
MCR p15, 4, <Rt>, c0, c0, 0; Write Virtualization Processor ID Register
Related information
4.3.1 Main ID Register, EL1
Non-ConfidentialPDF file icon PDF versionARM DDI0488F
Copyright © 2013, 2014 ARM. All rights reserved.