4.3.30 System Control Register, EL1

The SCTLR_EL1 characteristics are:

Purpose
Provides top-level control of the system, including its memory system at EL1 in AArch64 state.
Usage constraints
The accessibility of the SCTLR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The SCTLR_EL1 is:
  • A 32-bit register in AArch64 state.
  • Architecturally mapped to the Non-secure AArch32 SCTLR register.
Attributes
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the SCTLR_EL1 bit assignments.
Figure 4-28 SCTLR_EL1 bit assignments
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The following table shows the SCTLR_EL1bit assignments.

Table 4-44 SCTLR_EL1 bit assignments

Bits Name Function
[31:30] - Reserved, RES0.
[29:28] - Reserved, RES1.
[27] - Reserved, RES0.
[26] UCI
Enables EL0 access to the DC CVAU, DC CIVAC, DC CVAC and IC IVAU instructions in AArch64 state. The values are:
0EL0 access disabled. This is the reset value.
1EL0 access enabled.
[25] EE
Exception endianness. Indicates the endianness of the translation table data for the translation table lookups. The EE bit is permitted to be cached in a TLB. The values are:
0Little-endian.
1Big-endian.
[24] E0E
Endianness of explicit data access at EL0. The values are:
0Explicit data accesses at EL0 are little-endian. This is reset value.
1Explicit data accesses at EL0 are big-endian.
[23:22] - Reserved, RES1.
[21] - Reserved, RES0.
[20] - Reserved, RES1.
[19] WXN
Write permission implies Execute Never (XN). You can use this bit to require all memory regions with write permissions are treated as XN. The WXN bit is permitted to be cached in a TLB. The values are:
0Regions with write permission are not forced to be XN. This is the reset value.
1Regions with write permissions are forced to be XN.
[18] nTWE
WFE non-trapping. The values are:
0A WFE instruction executed at EL0 that causes suspended execution as if the event register is not set and there is no pending WFE wake-up event, is treated as an exception with error code of 0x1.
1WFE instructions executed as normal. This is the reset value.
Conditional WFE instructions that fail their condition do not cause an exception if this bit is 0.
[17] - Reserved, RES0.
[16] nTWI
WFI non-trapping. The values are:
0A WFI instruction executed at EL0 that causes suspended execution as if there is no pending WFI wake-up event, is treated as an exception with error code of 0x1.
1WFI instructions executed as normal. This is the reset value.
Conditional WFI instructions that fail their condition do not cause an exception if this bit is 0.
[15] UCT
Enables EL0 access to the CTR_EL0 register in AArch64 state. The values are:
0Disables EL0 access to the CTR_EL0 register. This is the reset value.
1Enables EL0 access to the CTR_EL0 register.
[14] DZE
Enables access to the DC ZVA instruction at EL0. The values are:
0Disables execution access to the DC ZVA instruction at EL0. Access is treated as UNDEFINED. This is the reset value.
1Enables execution access to the DC ZVA instruction at EL0.
[13] - Reserved, RES0.
[12] I
Instruction cache enable. The values are:
0Instruction caches disabled. This is the reset value.
1Instruction caches enabled.
[11] - Reserved, RES1.
[10] - Reserved, RES0.
[9] UMA
User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64. The values are:
0Disables access to the interrupt masks from EL0.
1Enables access to the interrupt masks from EL0.
[8] SED
SETEND instruction disable. The values are:
0The SETEND instruction is enabled. This is the reset value.
1The SETEND instruction is UNALLOCATED.
[7] ITD
IT instruction disable. The values are:
0The IT instruction functionality is enabled. This is the reset value.
1
All encodings of the IT instruction are UNDEFINED when either:
  • hw[3:0] are not equal to 0b1000.
  • IT instructions with a subsequent 32-bit instruction.
  • Subsequent PC reading or writing instruction.
[6] THEE
ThumbEE enable:
0
ThumbEE is not implemented.
[5] CP15BEN
AArch32 CP15 barrier enable. The values are:
0CP15 barrier operations disabled. Their encodings are UNDEFINED.
1CP15 barrier operations enabled. This is the reset value.
[4] SA0
Enable EL0 Stack Alignment check. When set, use of the Stack Pointer as the base address in a load/store instruction at EL0 must align to a 16-byte boundary, or a Stack Alignment Fault exception is raised. The values are:
0Disable EL0 Stack Alignment check.
1Enable EL0 Stack Alignment check. This is the reset value.
[3] SA
Enable Stack Alignment check. When set, use of the Stack Pointer as the base address in a load/store instruction at the Exception level of this register must align to a 16-byte boundary, or a Stack Alignment Fault exception is raised. The values are:
0Disable Stack Alignment check.
1Enable Stack Alignment check. This is the reset value.
[2] C
Cache enable. The values are:
0Data and unified caches disabled. This is the reset value.
1Data and unified caches enabled.
[1] A
Alignment check enable. The values are:
0Alignment fault checking disabled. This is the reset value.
1Alignment fault checking enabled.
[0] M
MMU enable. The values are:
0EL1 and EL0 stage 1 MMU disabled. This is the reset value.
1EL1 and EL0 stage 1 MMU enabled.
To access SCTLR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, SCTLR_EL1; Read EL1 System Control Register
MSR SCTLR_EL1, <Xt>; Write EL1 System Control Register
Related information
4.5.5 System Control Register
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