The CPACR_EL1 characteristics are:
- Controls access to trace functionality and access
to registers associated with Floating-point and Advanced SIMD execution.
- Usage constraints
The accessibility of the CPACR_EL1 by Exception
||EL3(SCR.NS = 1)
||EL3(SCR.NS = 0)
The CPACR_EL1 is:
register in AArch64 state.
- Architecturally mapped to the Non-secure AArch32 CPACR register.
- See the register summary in Table 4-4 AArch64 other System registers.
The following figure shows the
CPACR_EL1 bit assignments.
Figure 4-29 CPACR_EL1 bit assignments
The following table shows the CPACR_EL1
Table 4-45 CPACR_EL1 bit assignments
Traps trace functionality to EL1 when
executing from EL0 or EL1. The value is:
- System register access to trace functionality is
not supported. This bit is RES0.
Traps instructions that access registers
associated with floating-point and SIMD execution to trap to EL1
when executed from EL0 or EL1. The possible values are:
- Trap any instruction in EL0 or EL1 that use registers
associated with floating-point and Advanced SIMD execution. The
reset value is
- Trap any instruction in EL0 that use registers associated
with floating-point and Advanced SIMD execution. Instructions in
EL1 are not trapped.
- No instructions are trapped.
To access the CPACR_EL1 in AArch64 state, read or write the
MRS <Xt>, CPACR_EL1; Read EL1 Architectural Feature Access Control Register
MSR CPACR_EL1, <Xt>; Write EL1 Architectural Feature Access Control Register