4.3.34 Hypervisor Configuration Register, EL2

The HCR_EL2 characteristics are:
Purpose
Provides configuration control for virtualization, including whether various Non-secure operations are trapped to EL2.
Usage constraints
The accessibility of the HCR_EL2 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW
Configurations
The HCR_EL2 is architecturally mapped as follows:
  • [63:32] to the AArch32 HCR2 register.
  • [31:0] to the AArch32 HCR register.
Attributes
See the register summary in Table 4-13 AArch64 virtualization registers.
The following figure shows the HCR_EL2 bit assignments.
Figure 4-31 HCR_EL2 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the HCR_EL2 bit assignments.

Table 4-47 HCR_EL2 bit assignments

Bits Name Function
[63:34] - Reserved, RES0.
[33] ID
Disables stage 2 Instruction Cache. When HCR_EL2.VM is 1, this forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regimes. The values are:
0
Has no effect on stage 2 EL1/EL0 translation regime for instruction accesses. This is the reset value.
1
Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regime.
[32] CD
Disables stage 2 data cache. When HCR_EL2.VM is 1, this forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regimes. The values are:
0
Has no effect on stage 2 EL1/EL0 translation regime for data access or translation table walks. This is the reset value.
1
Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regime.
[31] RW
Register width control for lower Exception levels. The values are:
0
Lower levels are all AArch32. This is the reset value.
1
EL1 is AArch64. EL0 is determined by the register width described in the current processing state when executing at EL0.
[30] TRVM
Trap Read of Virtual Memory controls. When 1, this causes reads to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers the following registers:
AArch32
SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.
AArch64
SCTLR_EL1, TTBR0_EL1, TTBR1_EL1, TCR_EL1, ESR_EL1, FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1, and CONTEXTIDR_EL1.
The reset value is 0.
[29] HCD Disables Hyp call. The processor implements EL3. This bit is RES0.
[28] TDZ
Traps DC ZVA instruction. The values are:
0
DC ZVA instruction is not trapped.
1
DC ZVA instruction is trapped to EL2 when executed in Non-secure EL1 or EL0.
[27] TGE
Traps general exceptions. If this bit is set, and SCR_EL3.NS is set, then:
  • All EL1 exceptions are routed to EL2.
  • For EL1, the SCTLR_EL1.M bit is treated as 0 regardless of its actual state other than the purpose of reading the bit.
  • The HCR_EL2.FMO, HCR_EL2.IMO, and HCR_AMO bits are treated as 1 regardless of their actual state other than for the purpose of reading the bits.
  • All virtual interrupts are disabled.
  • Any IMPLEMENTATION DEFINED mechanisms for signaling virtual interrupts are disabled.
  • An exception return to EL1 is treated as an illegal exception return.
[26] TVM
Trap Virtual Memory controls. When 1, this causes writes to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers the following registers:
AArch32
SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.
AArch64
SCTLR_EL1, TTBR0_EL1, TTBR1_EL1, TCR_EL1, ESR_EL1, FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1, and CONTEXTIDR_EL1.
The reset value is 0.
[25] TTLB
Trap TLB maintenance instructions. When 1, this causes TLB maintenance instructions executed from EL1 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:
AArch32
TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, ITLBIALL, DTLBIALL, TLBIALL, ITLBIMVA, DTLBIMVA, TLBIMVA, ITLBIASID, DTLBIASID, TLBIASID, TLBIMVAA, TLBIMVALIS, TLBIMVAALIS, TLBIMVAL, and TLBIMVAAL.
AArch64
TLBI VAMLLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1, TLBI VALE1, TLBI VAALE1, TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, and TLBI VAALE1IS.
The reset value is 0.
[24] TPU
Trap Cache maintenance instructions to Point of Unification. When 1, this causes Cache maintenance instructions to the point of unification executed from EL1 or EL0 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:
AArch32
ICIMVAU, ICIALLU, ICIALLUIS, and DCCMVAU.
AArch64
IC IVAU, IC IALLU, IC IALLUIS, and DC CVAU.
The reset value is 0.
[23] TPC
Trap Data/Unified Cache maintenance operations to point of coherency. When 1, this causes Data or Unified Cache maintenance instructions by address to the point of coherency executed from EL1 or EL0 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:
AArch32
DCIMVAC, DCCIMVAC, and DCCMVAC.
AArch64
DC IVAC, DC CIVAC, and DC CVCA.
The reset value is 0.
[22] TSW
Trap Data/Unified Cache maintenance operations by Set/Way. When 1, this causes Data or Unified Cache maintenance instructions by set/way executed from EL1 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:
AArch32
DCISW, DCCSW, and DCCISW.
AArch64
DC ISW, DC CSW, and DC CISW.
The reset value is 0.
[21] TACR
Traps Auxiliary Control registers. The values are:
0
Accesses to the Auxiliary Control registers are not trapped.
1
Accesses to the ACTLR in AArch32 state or the ACTLR_EL1 in AArch64 state from EL1 are trapped to EL2.
[20] TIDCP
Trap Implementation Dependent functionality. When 1, this causes accesses to the following instruction set space executed from EL1 to be trapped to EL2:
AArch32
All CP15 MCR and MRC instructions as follows:
  • CRn is 9, op1 is 0 to 7, CRm is c0, c1, c2, c5, c6, c7, or c8, and op2 is 0 to 7.
  • CRn is 10, op1 is 0 to 7, CRm is c0, c1, c4, or c8, and op2 is 0 to 7.
  • CRn is 11, op1 is 0 to 7, CRm is c0 to c8, or c15, and op2 is 0 to 7.
AArch64
Reserved control space for IMPLEMENTATION DEFINED functionality.
Accesses from EL0 are UNDEFINED. The reset value is 0.
[19] TSC
Traps SMC instruction. The values are:
0
SMC instruction is not trapped.
1
SMC instruction executed in EL1 is trapped to EL2 for AArch32 and AArch64 states.
[18] TID3
Trap ID Group 3. When 1, this causes reads to the following registers executed from EL1 to be trapped to EL2:
AArch32
ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0, ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, and MVFR2 and MRC instructions to the following locations:
  • op1 is 0, CRn is 0, CRm is c3, c4, c5, c6, or c7, and op2 is 0 or 1.
  • op1 is 0, CRn is 0, CRm is c3, and op2 is 2.
  • op1 is 0, CRn is 0, CRm is 5, and op2 is 4 or 5.
AArch64
ID_PFR0_EL1, ID_PFR1_EL1, ID_DFR0_EL1, ID_AFR0_EL1, ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, ID_ISAR5_EL1, MVFR0_EL1, MVFR1_EL1, MVFR2_EL1, ID_AA64PFRn_EL1, ID_AA64DFRn_EL1, ID_AA64ISARn_EL1, ID_AA64MMFRn_EL1, and ID_AA64AFRn_EL1.
The reset value is 0.
[17] TID2
Trap ID Group 2. When 1, this causes reads or writes to CSSELR/CSSELR_EL1, to the following registers executed from EL1 or EL0 that are UNDEFINED to be trapped to EL2:
AArch32
CTR, CCSIDR, CLIDR, and CSSELR.
AArch64
CTR_EL0, CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1.
The reset value is 0.
[16] TID1
Trap ID Group 1. When 1, this causes reads to the following registers executed from EL1 to be trapped to EL2:
AArch32
TCMTR, TLBTR, AIDR, and REVIDR.
AArch64
AIDR_EL1, and REVIDR_EL1.
The reset value is 0.
[15] TID0
Trap ID Group 0. When 1, this causes reads to the following registers executed from EL1 or EL0 that are UNDEFINED to be trapped to EL2:
AArch32
FPSID and JIDR.
AArch64
None.
The reset value is 0.
[14] TWE
Traps WFE instruction if it would cause suspension of execution. For example, if there is no pending WFE event:
0
WFE instruction is not trapped.
1
WFE instruction executed in EL1 or EL0 is trapped to EL2 for AArch32 and AArch64 states.
[13] TWI
Traps WFI instruction if it would cause suspension of execution. For example, if there is no pending WFI event:
0
WFI instruction is not trapped.
1
WFI instruction executed in EL1 or EL0 is trapped to EL2 for AArch32 and AArch64 states.
[12] DC
Default Cacheable. When this bit is set to 1 the memory type and attributes determined by stage 1 translation is Normal, Non-shareable, Inner Write-Back Write-Allocate, Outer Write-Back Write-Allocate.
When executing in Non-secure EL0 or EL1 and the HCR_EL2.DC bit is set, the behavior of processor is consistent with the behavior when:
  • The SCTLR_EL1.M bit is clear, regardless of the actual value of the SCTLR.M bit.
    • An explicit read of the SCTLR_EL1.M bit returns its actual value.
  • The HCR_EL2.VM bit is set, regardless of the actual value of the HCR_EL2.VM bit.
    • An explicit read of the HCR_EL2.VM bit returns its actual value.
The reset value is 0.
[11:10] BSU
Barrier shareability upgrade. Determines the minimum shareability domain that is supplied to any barrier executed from EL1 or EL0. The values are:
0b00
No effect.
0b01
Inner Shareable.
0b10
Outer Shareable.
0b11
Full system.
This value is combined with the specified level of the barrier held in its instruction, according to the algorithm for combining shareability attributes.
[9] FB
Force broadcast. When 1, this causes the following instructions to be broadcast within the Inner Shareable domain when executed from Non-secure EL1:
AArch32
ITLBIALL, DTLBIALL, TLBIALL, ITLBIMVA, DTLBIMVA, TLBIMVA, ITLBIASID, DTLBIASID, TLBIASID, TLBIMVAA, BPIALL, and ICIALLU.
AArch64
TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1, TLBI VALE1, TLBI VAALE1, and IC IALLU.
The reset value is 0.
[8] VSE
Virtual System Error/Asynchronous Abort. The values are:
0
Virtual System Error/Asynchronous Abort is not pending by this mechanism.
1
Virtual System Error/Asynchronous Abort is pending by this mechanism.
The virtual System Error/Asynchronous Abort is only enabled when the HCR_EL2.AMO bit is set.
[7] VI
Virtual IRQ interrupt. The values are:
0
Virtual IRQ is not pending by this mechanism.
1
Virtual IRQ is pending by this mechanism.
The virtual IRQ is only enabled when the HCR_EL2.IMO bit is set.
[6] VF
Virtual FIQ interrupt. The values are:
0
Virtual FIQ is not pending by this mechanism.
1
Virtual FIQ is pending by this mechanism.
The virtual FIQ is only enabled when the HCR_EL2.FMO bit is set.
[5] AMO
Asynchronous abort and error interrupt routing. The values are:
0
Asynchronous external Aborts and SError Interrupts while executing at Exception levels lower than EL2 are not taken at EL2. Virtual System Error/Asynchronous Abort is disabled.
1
Asynchronous external Aborts and SError Interrupts while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_EL3.EA bit to EL3. Virtual System Error/Asynchronous Abort is enabled.
[4] IMO
Physical IRQ routing. The values are:
0
Physical IRQ while executing at Exception levels lower than EL2 are not taken at EL2. Virtual IRQ interrupt is disabled.
1
Physical IRQ while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_EL3.IRQ bit to EL3. Virtual IRQ interrupt is enabled.
[3] FMO
Physical FIQ routing. The values are:
0
Physical FIQ while executing at Exception levels lower than EL2 are not taken at EL2. Virtual FIQ interrupt is disabled.
1
Physical FIQ while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_EL3.FIQ bit to EL3. Virtual FIQ interrupt is enabled.
[2] PTW Protected Table Walk. When this bit is set, if stage 2 translation of a translation table access, made as part of a stage 1 translation table walk at EL0 or EL1, maps to Strongly-ordered or Device memory, the access is faulted as a stage 2 Permission fault.
[1] SWIO
Set/Way Invalidation Override. EL1 execution of the data cache invalidate by set/way instruction is treated as data cache clean and invalidate by set/way. When this bit is set:
  • DCISW is treated as DCCISW when in AArch32 state
  • DC ISW is treated as DC CISW when in AArch64 state.
[0] VM
Enables second stage of translation. The values are:
0
Disables second stage translation.
1
Enables second stage translation for execution in EL1 and EL0.
To access the HCR_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, HCR_EL2; Read EL2 Hypervisor Configuration Register
MRS HCR_EL2, <Xt>; Write EL2 Hypervisor Configuration Register
Related information
4.5.11 Hyp Configuration Register 2
4.5.10 Hyp Configuration Register
Non-ConfidentialPDF file icon PDF versionARM DDI0488F
Copyright © 2013, 2014 ARM. All rights reserved.