The CPTR_EL3 characteristics are:
- Purpose
- Controls trapping to EL3 for accesses to the CPACR_EL1
register, trace functionality and registers associated with floating-point
and SIMD execution. Also controls EL3 access to this functionality.
- Usage constraints
The accessibility of the CPTR_EL3 by Exception level
is:
| EL0 |
EL1(NS) |
EL1(S) |
EL2 |
EL3(SCR.NS = 1) |
EL3(SCR.NS = 0) |
| - |
- |
- |
- |
RW |
RW |
- Configurations
- The CPTR_EL3 is a 32-bit register.
- Attributes
- See the register summary in Table 4-12 AArch64 security registers.
The following figure shows the
CPTR_EL3 bit assignments.
Figure 4-36 CPTR_EL3 bit assignments
The following table shows the CPTR_EL3
bit assignments.
Table 4-52 CPTR_EL3 bit assignments
| Bits |
Name |
Function |
| [63:32] |
- |
Reserved, RES0. |
| [31] |
TCPAC |
Traps direct access to CPACR_EL1 from
EL1 to EL3. The possible values are:
- 0
- Access to CPACR_EL1 is not trapped. This is the
reset value.
- 1
- Access to CPACR_EL1 is trapped.
|
| [30:21] |
- |
Reserved, RES0. |
| [20] |
TTA |
This bit is RES0.
The processor does not support System register access to trace functionality. |
| [19:11] |
- |
Reserved, RES0. |
| [10] |
TFP |
Traps instructions that access registers
associated with floating-point and Advanced SIMD execution from
a lower Exception level to EL3, unless trapped to EL1. The possible
values are:
- 0
- Instructions that access registers associated with
floating-point and Advanced SIMD execution are not trapped.
- 1
- Instructions that access registers associated with
floating-point and Advanced SIMD execution are trapped. This is
the reset value.
|
| [9:0] |
- |
Reserved, RES0. |
To access the CPTR_EL3 in AArch64 state, read or write the
register with:
MRS <Xt>, CPTR_EL3; Read EL3 Architectural Feature Trap Register
MSR CPTR_EL3, <Xt>; Write EL3 Architectural Feature Trap Register
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