4.3.41 Translation Control Register, EL1

The TCR_EL1 characteristics are:

Purpose
Controls which Translation Base Register defines the base address register for a translation table walk required for stage 1 translation of a memory access from EL0 or EL1. Also controls the translation table format and holds cacheability and shareability information.
Usage constraints
The accessibility of the TCR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
TCR_EL1[31:0] is architecturally mapped to the Non-secure AArch32 TTBCR register.
Attributes
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the TCR_EL1 bit assignments.
Figure 4-37 TCR_EL1 bit assignments
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The following table shows the TCR_EL1 bit assignments.

Table 4-53 TCR_EL1 bit assignments

Bits Name Function
[63:39] - Reserved, RES0.
[38] TBI1
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the TTBR1 region. The values are:
0Top byte used in the address calculation.
1Top byte ignored in the address calculation.
[37] TBI0
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the TTBR0 region. The values are:
0Top byte used in the address calculation.
1Top byte ignored in the address calculation.
[36] AS
ASID size. The values are:
08-bit.
116-bit.
[35] - Reserved, RES0.
[34:32] IPS
Intermediate Physical Address Size. The possible values are:
0b00032-bit, 4GBytes.
0b00136-bit, 64GBytes.
0b01040-bit, 1TByte.
0b01142-bit, 4TBytes.
0b10044-bit, 16TBytes.
0b10148-bit, 256TBytes.
[31] - Reserved, RES1.
[30] TG1
TTBR1_EL1 granule size. The values are:
04KB.
164KB.
[29:28] SH1
Shareability attribute for memory associated with translation table walks using TTBR1. The values are:
0b00Non-shareable.
0b01Reserved.
0b10Outer Shareable.
0b11Inner Shareable.
[27:26] ORGN1
Outer cacheability attribute for memory associated with translation table walks using TTBR1. The values are:
0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[25:24] IRGN1
Inner cacheability attribute for memory associated with translation table walks using TTBR1. The values are:
0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[23] EPD1
Translation table walk disable for translations using TTBR1. Controls if a translation table walk is performed on a TLB miss for an address that is translated using TTBR1. The values are:
0Perform translation table walk using TTBR1.
1A TLB miss on an address translated from TTBR1 generates a Translation fault. No translation table walk is performed.
[22] A1
Selects whether TTBR0 or TTBR1 defines the ASID. The values are:
0TTBR0.ASID defines the ASID.
1TTBR1.ASID defines the ASID.
[21:16] T1SZ Size offset of the memory region addressed by TTBR1. The region size is 2(64–TSIZE) bytes.
[15] - Reserved, RES0.
[14] TG0
TTBR0_EL1 granule size. The values are:
04KB.
164KB.
[13:12] SH0
Shareability attribute for memory associated with translation table walks using TTBR0. The values are:
0b00Non-shareable.
0b01Reserved.
0b10Outer Shareable.
0b11Inner Shareable.
[11:10] ORGN0
Outer cacheability attribute for memory associated with translation table walks using TTBR0. The values are:
0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0
Inner cacheability attribute for memory associated with translation table walks using TTBR0. The values are:
0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] - Reserved, RES0.
[5:0] T0SZ
Size offset of the memory region addressed by TTBR0. The region size is 2(64–TSIZE) bytes.
To access the TCR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, TCR_EL1; Read EL1 Translation Control Register
MSR TCR_EL1, <Xt>; Write EL1 Translation Control Register
Related information
4.5.15 Translation Table Base Control Register
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