4.3.45 Translation Table Base Register 0, EL3

The TTBR0_EL3 characteristics are:
Holds the base address of the translation table for the stage 1 translation of memory accesses from EL3.
Usage constraints
The accessibility to the TTBR0_EL3 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - - RW RW
TTBR0_EL3 is mapped to the Secure AArch32 TTBR0 register.
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the TTBR0_EL3 bit assignments.
Figure 4-41 TTBR0_EL3 bit assignments
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The following table shows the TTBR0_EL3 bit assignments.

Table 4-57 TTBR0_EL3 bit assignments

Bits Name Function
[63:48] - Reserved, RES0.
[47:10] BADDR Translation table base address. Defining the translation table base address width.
[9:0] - Reserved, UNK/RES0.
To access the TTBR0_EL3 in AArch64 state, read or write the register with:
MRS <Xt>, TTBR0_EL3; Read EL3 Translation Table Base Register 0
MSR TTBR0_EL3, <Xt>; Write EL3 Translation Table Base Register 0
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