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Home > System Control > AArch64 register descriptions > L2 Control Register, EL1 |
The L2CTLR_EL1 characteristics are:
ISB
to ensure
the MMU disable operation is complete, then execute a DSB
to drain
previous memory transactions.Table 4-69 L2CTLR_EL1 bit assignments
Bits | Name | Function |
---|---|---|
[31] | L2RSTDISABLE monitor | Monitors the L2 hardware reset disable signal, L2RSTDISABLE. The values are:
This bit is read-only. The primary input L2RSTDISABLE controls the reset value.
|
[30:26] | - | Reserved, RES0. |
[25:24] | Number of processors | Number of processors present. These bits are read-only and set
to the number of processors present in the implementation. The values are:
|
[23] | - | Reserved, RES0. |
[22] | L1 Cache ECC and Parity protection | This bit is read-only and is set if the
processor
implementation supports L1 cache ECC and parity protection. The L1 cache ECC and
parity protection is a configurable implementation option in Cortex-A57
processor.
The values are:
|
[21] | ECC and parity enable | ECC and parity enable. The values are:
If Cortex-A57 is implemented with L1 Cache ECC and parity protection,
L2CTLR[21] can be programmed to enable or disable both L1 and L2 ECC and parity
protection.
If Cortex-A57 is implemented with no L1 Cache ECC and parity
protection, L2CTLR[21] can be programmed to enable or disable only L2 ECC and
parity protection.
|
[20] | Data inline ECC enable, only applies if ECC is enabled | Force inline ECC for Instruction Fetch (IF) and
Load/Store (LS) read requests that hit the L2 cache increasing the
L2 hit latency by 2 cycles. Avoids requirement of flushing requests associated
with L2 cache single-bit ECC errors. The possible values are:
|
[19:14] | - | Reserved, RES0. |
[13] | L2 arbitration slice | L2 arbitration slice. This is a read-only bit that is set if the
L2 arbitration slice is present in the implementation. The values are:
|
[12] | L2 Tag RAM slice | L2 Tag RAM slice. This is a read-only bit that is set if the Tag
RAM slice is present in the implementation. The values are:
|
[11:10] | L2 Data RAM slice | L2 Data RAM slice. These are read-only bits that are set to the
number of Data RAM slices present in the implementation. The values are:
|
[9] | L2 Tag RAM setup | L2 Tag RAM setup. The values are:
|
[8:6] | L2 Tag RAM latency | L2 Tag RAM latency. The L2 Tag RAM programmable setup and latency bits only affect the
L2 Tag RAM. See 7.2.5 Register slice support for large cache
sizes for more information. The
possible values are:
|
[5] | L2 Data RAM setup | L2 Data RAM setup. The values are:
|
[4:3] | - | Reserved, RES0.
|
[2:0] | L2 Data RAM latency | L2 Data RAM latency.c The L2 Data RAM programmable setup &
latency bits affect only the L2 Data RAM. See 7.2.5 Register slice support for large cache
sizes
for more information. The values are:
|
MRS <Xt>, S3_1_c11_c0_2; Read L2 Control Register MSR S3_1_c11_c0_2, <Xt>; Write L2 Control Register
MRC p15, 1, <Rt>, c9, c0, 2; Read L2 Control Register MCR p15, 1, <Rt>, c9, c0, 2; Write L2 Control Register