The RMR_EL3 characteristics are:
- Purpose
- Controls the Execution state that the processor
boots into and allows request of a Warm reset.
- Usage constraints
The accessibility to the RMR_EL3 by Exception level
is:
| EL0 |
EL1(NS) |
EL1(S) |
EL2 |
EL3(SCR.NS = 1) |
EL3(SCR.NS = 0) |
| - |
- |
- |
- |
RW |
RW |
- Configurations
The RMR_EL3 is
- Common to the Secure and Non-secure states.
- Architecturally mapped to the AArch32 RMR register.
- Attributes
Write access to RMR_EL3 is disabled when the CP15SDISABLE signal is HIGH
and EL3 is using AArch32.
The following figure shows the
RMR_EL3 bit assignments.
Figure 4-53 RMR_EL3 bit assignments
The following table shows the RMR_EL3
bit assignments.
Table 4-72 RMR_EL3 bit assignments
| Bits |
Name |
Function |
| [31:2] |
- |
Reserved, RES0. |
| [1] |
RR |
Reset Request. The values are:
- 0
- This is the reset value. It is set to zero by either
a Cold or Warm reset.
- 1
- Requests a Warm reset.
|
| [0] |
AA64a |
Determines the Execution state at processor
boot time. The values are:
- 0
- AArch32 state.
- 1
- AArch64 state.
If
software requests a Warm reset by setting RR=1 then it can use the
AA64 bit to change Execution state.
|
To access the RMR_EL3 in AArch64 state, read or write the
register with:
MRS <Xt>, RMR_EL3; Read EL3 Reset Management Register
MSR RMR_EL3, <Xt>; Write EL3 Reset Management Register
To access the RMR, in AArch32 state, read or write the CP15
register with:
MRC p15, 0, <Rt>, c12, c0, 2; Read Reset Management Register
MCR p15, 0, <Rt>, c12, c0, 2; Write Reset Management Register
PDF version