4.3.63 Data L1 Data n Register, EL1

The DL1DATAn_EL1, where n is from 0 to 4, characteristics are:
Purpose
Holds the data side L1 or L2 array information returned by the RAMINDEX write operation.

Note

Because the Data, Tag, and TLB arrays are greater than 32-bit wide, the processor contains multiple DL1DATA registers, to hold the array information.
Usage constraints
The accessibility to the DL1DATAn_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The DL1DATAn_EL1 is:
  • Common to the Secure and Non-secure states.
  • A 32-bit register in AArch64 state.
  • Architecturally mapped to the AArch32 DL1DATAn registers.
Attributes
See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the DL1DATAn_EL1 bit assignments.
Figure 4-55 DL1DATA
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the DL1DATAn_EL1 bit assignments.

Table 4-74 DL1DATAn_EL1 bit assignments

Bits Name Function
[31:0] Data Holds the data side L1 or L2 array information
To access the DL1DATAn_EL1 in AArch64 state, read or write the registers with:
MRS <Xt>, s3_0_c15_c1_n; Read EL1 Data L1 Data n Register
MSR s3_0_c15_c1_n, <Xt>; Write EL1 Data L1 Data n Register
n is 0, 1, 2, 3, or 4 for Opcode2 of the DL1DATAn_EL1 registers.
To access the DL1DATAn in AArch32 state, read or write the CP15 registers with:
MRC p15, 0, <Rt>, c15, c1, n; Read Data L1 Data n Register
MCR p15, 0, <Rt>, c15, c1, n; Write Data L1 Data n Register
n is 0, 1, 2, 3, or 4 for Opcode2 of the DL1DATAn registers.
Related information
4.3.64 RAM Index operation
Non-ConfidentialPDF file icon PDF versionARM DDI0488F
Copyright © 2013, 2014 ARM. All rights reserved.