4.3.65 L2 Auxiliary Control Register, EL1

The L2ACTLR_EL1 characteristics are:
PurposeProvides IMPLEMENTATION DEFINED configuration and control options for the L2 memory system. There is one L2 Auxiliary Control Register for the Cortex-A57 processor.
Usage constraints
The accessibility to the L2ACTLR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RWa RWb RW RW

Note

The L2ACTLR_EL1 must be set statically and not dynamically changed.
The L2 Auxiliary Control Register can only be written when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE, CHI, or ACP traffic begins.
If the register must be modified after a powerup reset sequence, you must to idle the L2 memory system with the following sequence:
  1. Disable the MMU from each core followed by an ISB to ensure the MMU disable operation is complete, then execute a DSB to drain previous memory transactions.
  2. Ensure that the system has no outstanding ACE AC channel or CHI RXRSP coherence requests to the Cortex-A57 processor.
  3. Ensure that the system has no outstanding ACP requests to the Cortex-A57 processor.
When the L2 is idle, the processor can update the L2 Auxiliary Control Register followed by an ISB. After the L2 Auxiliary Control Register is updated, you can enable the MMUs and normal ACE or CHI and ACP traffic can resume.
Configurations
The L2ACTLR_EL1 is:
  • Common to the Secure and Non-secure states.
  • A 32 bit register in AArch64 state.
  • Architecturally mapped to the AArch32 L2ACTLR register.
AttributesSee the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the L2ACTLR_EL1 bit assignments.
Figure 4-72 L2ACTLR_EL1 bit assignments
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The following table shows the L2ACTLR_EL1 bit assignments.

Table 4-76 L2ACTLR_EL1 bit assignments

Bits Name Function
[31:29] - Reserved, RES0.
[28] Force L2 tag bank clock enable active
Forces L2 tag bank clock enable active:
0Does not prevent the clock generator from stopping the L2 tag bank clock. This is the reset value.
1Prevents the clock generator from stopping the L2 tag bank clock.
This bit applies to each of the two L2 cache tag bank clocks.
If the L2 dynamic retention feature is used then this bit must be zero. See L2 RAMs dynamic retention.
[27]c Force L2 logic clock enable active
Forces L2 logic clock enable active:
0Does not prevent the clock generator from stopping the L2 logic clock. This is the reset value.
1Prevents the clock generator from stopping the L2 logic clock.
If the L2 dynamic retention feature is used then this bit must be zero. See L2 RAMs dynamic retention.
[26]c Force L2, GIC, Timer RCG enables active
Forces L2, GIC CPU interface, and Timer Regional Clock Gate (RCG) enables active:
0Enables L2, GIC CPU interface, and Timer RCGs for additional clock gating and potentially reduce dynamic power dissipation. This is the reset value.
1Forces L2, GIC CPU interface, and Timer RCG enables HIGH.
Setting this bit to 1 has no effect if the processor is configured to not include RCGs. See Regional clock gating.
[25]c Enable single issue across all tbnks when L2 arbitration replay threshold is reached
Enables single issue across all tag banks when the L2 arbitration replay threshold is reached, so that only one request can be active across both tag banks at any given time:
0Disables single issue across the tag banks when the L2 arbitration replay threshold is reached. This is the reset value.
1Enables single issue across the tag banks when the L2 arbitration replay threshold is reached.
[24] - Reserved, RES0.
[23]c Disable prefetch requests from ReadUnique transactions
Disables prefetch requests from ReadUnique transactions:
0Enables prefetch requests to be generated by ReadUnique transactions. This is the reset value.
1Disables prefetch requests to be generated by ReadUnique transactions.
[22]c Disable dynamic throttling of load/store prefetch requests
Disables dynamic throttling of load/store prefetch requests:
0Enables dynamic throttling of load/store prefetch requests. This is the reset value.
1Disables dynamic throttling of load/store prefetch requests.
[21:20] Disable throttling of L2 prefetch requests based on Fill/Evict Queue (FEQ) occupancy countd
Disables throttling of L2 prefetch requests based on FEQ occupancy count:
00
For a 16-entry FEQ implementation, enables throttling of L2 prefetch requests when FEQ count exceeds 12.
For a 20-entry FEQ implementation, enables throttling of L2 prefetch requests when FEQ count exceeds 16.
This is the reset value.
01
For a 16-entry FEQ implementation, enables throttling of L2 prefetch requests when FEQ count exceeds 10.
For a 20-entry FEQ implementation, enables throttling of L2 prefetch requests when FEQ count exceeds 14.
10
For a 16-entry FEQ implementation, enables throttling of L2 prefetch requests when FEQ count exceeds 8.
For a 20-entry FEQ implementation, enables throttling of L2 prefetch requests when FEQ count exceeds 12.
11Disables throttling of L2 prefetch requests based on FEQ occupancy count.
[19:18] Disable limit on NC/SO/Dev stores in Address Sequence Queue (ASQ)
Disables limit on NC/SO/Dev stores in ASQ:
00NC/SO/Dev stores limited to 12 entries in the ASQ. This is the reset value.
01NC/SO/Dev stores limited to 10 entries in the ASQ.
10NC/SO/Dev stores limited to 8 entries in the ASQ.
11There is no limit on NC/SO/Dev stores in the ASQ.
[17]c Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated
Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated:
0Enables L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated. This is the reset value.
1Disables L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated.
[16]c Enable replay threshold single issue
Enables replay threshold single issue:
0Disables replay threshold single issue. This is the reset value.
1Enables replay threshold single issue. If there are 32 consecutive transactions on a tag bank replay, then single issue is forced until a transaction successfully passes hazard checking.
[15]c Disable fast forwarding of data from ACE or CHI to LS and IF
Disables fast forwarding of data from ACE or CHI to LS and IF:
0Enables fast forwarding of data from ACE or CHI to LS and IF. This is the reset value.
1Disables fast forwarding of data from ACE or CHI to LS and IF.
[14] Enable UniqueClean evictions with data
Enables UniqueClean evictions with data:
0Disables UniqueClean evictions with data. This is the reset value if the multiprocessor implements the ACE interface.
1Enables UniqueClean evictions with data. This is the reset value if the multiprocessor implements the CHI interface.
[13]c Disable clean evict optimization
Disables clean evict optimization:
0Enables clean evict optimization. This is the reset value.
1Disables clean evict optimization.
[12] - Reserved, RES0.
[11]c Disable DSB with no DVM synchronization
Disables Data Synchronization Barrier (DSB) with no Distributed Virtual Memory (DVM) synchronization:
0
Enables DSB with no DVM synchronization. This is the reset value.
A DSB does not cause a DVM Sync message to occur. However, if a TLB maintenance operation, cache maintenance operation, or branch predictor maintenance operation occurs after the previous DSB then a DVM Sync message is generated regardless of the setting of this bit.
1Disables DSB with no DVM synchronization. Therefore, a DSB always causes a DVM Sync message to occur.
[10] Disable Non-secure debug array read
Disables Non-secure debug array read:
0Enables Non-secure debug array read access to Non-secure memory. This is the reset value.
1Disables Non-secure debug array read access.
[9] - Reserved, RES0.
[8]c Disable DVM and cache maintenance operation message broadcast
Disables DVM transactions and cache maintenance operation message broadcast:
0Enables DVM and cache maintenance operation message broadcast. This is the reset value.
1Disables DVM and cache maintenance operation message broadcast.
[7]c Enable hazard detect timeout
Enables hazard detect timeout:
0Disables hazard detect timeout. This is the reset value.
1Enables hazard detect timeout.
[6]c Disable ACE shareable or CHI snoopable transactions from master
Disables shareable or snoopable transactions from master:
0Enables ACE shareable or CHI snoopable transactions from master. This is the reset value.
1Disables ACE shareable or CHI snoopable transactions from master.
[5] - Reserved, RES0.
[4] Disable WriteUnique and WriteLineUnique transactions from master
Disables WriteUnique and WriteLineUnique transactions from master:
0Enables WriteUnique and WriteLineUnique transactions from master.
1Disables WriteUnique and WriteLineUnique transactions from master. This is the reset value.
[3] Disable clean/evict push to external
Disables clean/evict push to external:
0Enables clean/evict to be pushed out to external. This is the reset value if the processor implements the ACE interface.
1Disables clean/evict from being pushed to external. This is the reset value if the processor implements the CHI interface.
[2]c Limit to one request per tag bank
Limit to one request per tag bank:
0Normal behavior permitting parallel requests to the tag banks. This is the reset value.
1Limits to one request per tag bank.
[1]c Enable arbitration replay threshold timeout
Enables arbitration replay threshold timeout:
0Disables arbitration replay threshold timeout. This is the reset value.
1Enables arbitration replay threshold timeout.
[0]c Disable hardware prefetch forwarding
Disables hardware prefetch forwarding:
0Enables hardware prefetch forwarding. This is the reset value.
1Disables hardware prefetch forwarding.
To access the L2ACTLR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, s3_1_c15_c0_0; Read EL1 L2 Auxiliary Control Register
MSR s3_1_c15_c0_0, <Xt>; Write EL1 L2 Auxiliary Control Register
To access the L2ACTLR in AArch32 state, read or write the CP15 register with:
MRC p15, 1, <Rt>, c15, c0, 0; Read L2 Auxiliary Control Register
MCR p15, 1, <Rt>, c15, c0, 0; Write L2 Auxiliary Control Register
a Write access if ACTLR_EL3.L2ACTLR is 1 and ACTLR_EL2.L2ACTLR is 1, or ACTLR_EL3.L2ACTLR is 1 and the Secure SCR.NS is 0.
b Write access if ACTLR_EL3.L2ACTLR is 1.
c This bit is provided for debugging and characterization purpose only. For normal operation, ARM recommends that you do not change the value of this bit from its reset value.
d The 20-entry FEQ implementation option is available only in r1p0 and later revisions.
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