ARM® Cortex®-M7 Processor Technical Reference Manual

Revision r0p2

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-M7 processor
1.1.1. Features
1.1.2. Interfaces
1.1.3. Configuration options
1.2. Component blocks
1.2.1. Data Processing Unit
1.2.2. Prefetch Unit
1.2.3. Load Store Unit
1.2.4. Floating Point Unit
1.2.5. Nested Vectored Interrupt Controller
1.2.6. Wake-up Interrupt Controller
1.2.7. Memory System
1.2.8. Memory Protection Unit
1.2.9. Cortex-M7 Processor and PPB ROM tables
1.2.10. Cross Trigger Interface Unit
1.2.11. ETM
1.2.12. Debug and trace components
1.3. Interfaces
1.3.1. AHBP interface
1.3.2. AHBS interface
1.3.3. AHBD interface
1.3.4. External Private Peripheral Bus
1.3.5. ATB interfaces
1.3.6. TCM interface
1.3.7. Cross Trigger interface
1.3.8. MBIST interface
1.3.9. AXIM interface
1.4. Supported standards
1.4.1. ARM architecture
1.4.2. Bus architecture
1.4.3. Debug
1.4.4. Embedded Trace Macrocell
1.4.5. Floating Point Unit
1.5. Design process
1.6. Documentation
1.7. Product revisions
2. Programmers Model
2.1. About the programmers model
2.2. Modes of operation and execution
2.2.1. Operating modes
2.2.2. Operating states
2.2.3. Privileged access and unprivileged User access
2.3. Instruction set summary
2.3.1. Binary compatibility with other Cortex processors
2.4. System address map
2.4.1. Private peripheral bus
2.4.2. Unaligned accesses that cross regions
2.5. Exclusive monitor
2.6. Processor core registers
2.7. Exceptions
2.7.1. Exception handling
3. System Control
3.1. About system control
3.2. Register summary
3.3. Register descriptions
3.3.1. Auxiliary Control Register
3.3.2. CPUID Base Register
3.3.3. Cache Level ID Register
3.3.4. Cache Size ID Register
3.3.5. Cache Size Selection Register
3.3.6. Instruction and Data Tightly-Coupled Memory Control Registers
3.3.7. AHBP Control Register
3.3.8. L1 Cache Control Register
3.3.9. Auxiliary Bus Fault Status Register
3.3.10. Instruction Error bank Register 0-1
3.3.11. Data Error bank Register 0-1
3.3.12. AHB Slave Control Register
4. Initialization
4.1. About Initialization
4.1.1. Initializing the MPU
4.1.2. Initializing the FPU
4.1.3. Initializing and enabling the L1 cache
4.1.4. Disabling cache error checking and correction
4.1.5. Enabling the TCM
4.1.6. Preloading TCM
4.1.7. Enabling the TCM retry and read-modify-write
4.1.8. Enabling the AHBP interface
5. Memory System
5.1. About the memory system
5.2. Fault handling
5.2.1. Faults
5.2.2. Usage models
5.3. Memory types and memory system behavior
5.4. AXIM interface
5.4.1. AXI attributes and transactions
5.4.2. Identifiers for AXIM interface accesses
5.4.3. AXI privilege information
5.4.4. Write response
5.4.5. AXI extensions
5.4.6. Memory system implications for AXI accesses
5.4.7. AXIM interface transfers
5.5. AHB peripheral interface
5.5.1. AHBP interface transfers
5.5.2. AHBP semaphores
5.6. AHB slave interface
5.6.1. Restrictions on AHBS transactions
5.6.2. AHBS interface arbitration
5.7. TCM interfaces
5.7.1. TCM attributes and permissions
5.7.2. ITCM and D0TCM and D1TCM configuration
5.7.3. TCM arbitration
5.7.4. TCM interface protocol
5.8. L1 caches
5.8.1. Dynamic read allocate mode
5.8.2. Store buffer
5.8.3. Cache maintenance operations
5.8.4. Cache interaction with memory system
6. Memory Protection Unit
6.1. About the MPU
6.2. MPU functional description
6.3. MPU programmers model
7. Nested Vectored Interrupt Controller
7.1. About the NVIC
7.2. NVIC functional description
7.2.1. Low power modes
7.2.2. Level versus pulse interrupts
7.3. NVIC programmers model
7.3.1. Interrupt Controller Type Register
8. Floating Point Unit
8.1. About the FPU
8.2. FPU functional description
8.2.1. Modes of operation
8.2.2. Compliance with the IEEE 754 standard
8.2.3. Exceptions
8.3. FPU programmers model
9. Debug
9.1. About debug
9.1.1. Cortex-M7 Processor ROM table identification and entries
9.1.2. Cortex-M7 PPB ROM table identification and entries
9.1.3. System Control Space
9.1.4. Debug register summary
9.2. About the AHBD interface
9.3. About the FPB
9.3.1. FPB functional description
9.3.2. FPB programmers model
10. Cross Trigger Interface
10.1. About the CTI
10.2. Cortex-M7 CTI functional description
10.3. CTI programmers model
11. Data Watchpoint and Trace Unit
11.1. About the DWT
11.2. DWT functional description
11.3. DWT programmers model
12. Instrumentation Trace Macrocell Unit
12.1. About the ITM
12.2. ITM functional description
12.3. ITM programmers model
12.3.1. ITM Trace Privilege Register
13. Fault detection and handling
13.1. About fault detection and handling
13.1.1. RAM and logic protection
13.1.2. Analysis of errors
13.2. Cache RAM protection
13.2.1. Protection method
13.2.2. RAM protection summary
13.2.3. ECC codes
13.2.4. RAM configuration
13.2.5. Performance impact
13.3. Logic protection
A. Revisions

List of Tables

1.1. Implementation options
2.1. Memory regions
3.1. System control registers
3.2. SYST_CALIB inputs
3.3. ACTLR bit assignments
3.4. CPUID bit assignments
3.5. CLIDR bit assignments
3.6. CCSIDR bit assignments
3.7. CCSIDR encodings
3.8. CSSELR bit assignments
3.9. CM7_ITCMCR and CM7_DTCMCR bit assignments
3.10. CM7_AHBPCR bit assignments
3.11. CM7_CACR bit assignments
3.12. CM7_ABFSR bit assignments
3.13. IEBR0-1 bit assignments
3.14. DEBR0-1 bit assignments
3.15. CM7_AHBSCR bit assignments
5.1. Types of faults
5.2. Memory types and associated behavior
5.3. High performance AXIM attributes and transactions
5.4. Area optimized AXIM attributes and transactions
5.5. Cortex-M7 mode and APROT values
5.6. LDRB from Strongly-ordered or Device
5.7. LDRH from Strongly-ordered or Device memory
5.8. LDR or LDM1 from Strongly-ordered or Device memory
5.9. LDM2, Strongly-ordered or Device memory
5.10. STRB to Strongly-ordered or Device memory
5.11. STRH to Strongly-ordered or Device memory
5.12. STR or STM1 to Strongly-ordered or Device memory
5.13. STM5 to Strongly-ordered or Device memory to word 0 or 1
5.14. Linefill behavior on the AXI interface
5.15. Cache line write-back
5.16. STRH to Cacheable write-through or Non-cacheable Normal memory
5.17. STR to Cacheable write-through or Non-cacheable Normal memory
5.18. AXI transaction splitting, all six words in same cache line
5.19. AXI transaction splitting, data in two cache lines
5.20. Non-cacheable LDR or LDM1 crossing a cache line boundary
5.21. Non-cacheable STRH crossing a cache line boundary
5.22. AXI transactions for Strongly-ordered or Device type memory
5.23. AXI transactions for Non-cacheable Normal or Write-Through Cacheable memory
5.24. LDRB transfers
5.25. LDRH transfers
5.26. LDR or LDM of one register
5.27. LDM that transfers five registers
5.28. STRB transfers
5.29. STRH transfers
5.30. STR of one register
5.31. STM of five registers
5.32. LDRH transfers in Normal memory
5.33. LDR transfers in Normal memory
5.34. STRH transfers in Normal memory
5.35. STR transfers in Normal memory
5.36. Transaction properties
6.1. MPU registers
7.1. NVIC registers
7.2. ICTR bit assignments
8.1. Cortex-M7 ISA Support
8.2. Floating-point system registers
9.1. Cortex-M7 Processor ROM table identification values
9.2. Cortex-M7 Processor ROM table components
9.3. Cortex-M7 PPB ROM table identification values
9.4. Cortex-M7 PPB ROM table components
9.5. SCS identification values
9.6. Debug registers
9.7. FPB register summary
10.1. Trigger signals to the CTI
10.2. Trigger signals from the CTI
10.3. CTI register summary
11.1. DWT register summary
12.1. ITM register summary
12.2. ITM_TPR bit assignments
13.1. RAM protection summary
13.2. RAM configuration with or without ECC
A.1. Issue A
A.2. Differences between issue A and issue B

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A25 April 2014First release for r0p0
Revision B05 December 2014First release for r0p2
Copyright © 2014 ARM. All rights reserved.ARM DDI 0489B