5.7. AHB slave interface

The 32-bit AHB slave (AHBS) interface provides system access to the ITCM, D1TCM, and D0TCM. It includes arbitration logic to support simultaneous system and processor TCM access requests. The AHBS implements the AMBA 3 AHB-Lite protocol.

Writes are buffered in the processor Store Queue (SQ). The SQ also buffers software writes to the TCM and it performs all stores in-order. Reads can be performed to the TCM out-of-order with respect to buffered writes.

If there is a data dependency between a read and a software or AHBS buffered write, hazarding logic stalls the read and attempts to drain the SQ until there are no longer any dependencies. Writes continue to be performed in-order. Hazarding is performed at byte granularity.

All AHBS accesses are treated as being the same endianness as memory. No data swizzling is performed for reads or writes.

The AHBS interface can be used when the processor is in sleep state.

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