5.8.8. System access to TCM

The AHBS interface provides system access to the TCMs even when the processor is running. Arbitration between software and AHBS accesses to the TCMs is supported without requiring external TCM interface logic.

There is no hardware support for concurrency control between software and AHBS access to the TCMs. In particular, software exclusive accesses to the TCMs is only subject to the internal exclusive monitor that does not take AHBS accesses into account. This implies that the system must not perform AHBS accesses to any regions of TCM memory that are used with software exclusive accesses.

However, it is possible to share data coherently between software running on the processor and the system using the AHBS interface and with the following processor hardware guarantees:

The standard message passing model for data sharing can be used. The Arm architecture requires this model to work where coherency is supported, and is therefore portable to other Arm processors.

Table 5.38 shows the standard message passing software protocol.

Table 5.38. Standard message passing software protocol

Data generatorData consumer
STR <data>LDR <valid>
DMBLOOP until <valid> set
STR <valid>LDR <data>


  • Interrupt-based synchronization on the processor is possible when the AHBS interface is used to transfer system-generated data. In this model, an interrupt is generated when the AHBS completes the last data transfer. The first instruction in the ISR is guaranteed to observe any data items stored before, or on this transfer. In this case, the completion of the last AHBS access indicates global observability, instead of having to perform a software read of the location and waiting until it updates.

  • This scheme is not guaranteed to be supported on other Arm processors and you must use it with care when you require code portability.

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