13.3. TPIU programmers model

Table 13.1 shows the TPIU registers. Depending on the implementation of your processor, the TPIU registers might not be present, or the CoreSight TPIU might be present instead. Any register that is configured as not present reads as zero.

Table 13.1. TPIU registers

AddressNameTypeResetDescription
0xE0040000TPIU_SSPSRRO-[a]Supported Parallel Port Size Register
0xE0040004TPIU_CSPSRRW0x01Current Parallel Port Size Register
0xE0040010TPIU_ACPRRW0x0000Asynchronous Clock Prescaler Register
0xE00400F0TPIU_SPPRRW0x01Selected Pin Protocol Register
0xE0040300TPIU_FFSRRO0x08Formatter and Flush Status Register
0xE0040304TPIU_FFCRRW0x102Formatter and Flush Control Register
0xE0040308TPIU_FSCRRO0x00Formatter Synchronization Counter Register
0xE0040EE8TRIGGERRO0x0TRIGGER Register
0xE0040EECFIFO data 0RO0x0Integration ETM Data Register
0xE0040EF0ITATBCTR2RO0x0 Integration Test ATB Control Register 2
0xE0040EFCFIFO data 1RO0x0Integration ITM Data Register
0xE0040EF8ITATBCTR0RO0x0Integration Test ATB Control 0 Register
0xE0040F00ITCTRLRW0x0Integration Mode Control
0xE0040FA0CLAIMSETRW0xFClaim tag set
0xE0040FA4CLAIMCLRRW0x0Claim tag clear
0xE0040FC8DEVIDRO0xCA0/0xCA1Device Configuration Register
0xE0040FCCDEVTYPERO0x11Device Type Identifier Register
0xE0040FD0PID4RO0x04Peripheral identification registers
0xE0040FD4PID5RO0x00
0xE0040FD8PID6RO0x00
0xE0040FDCPID7RO0x00
0xE0040FE0PID0RO0xA9
0xE0040FE4PID1RO0xB9
0xE0040FE8PID2RO0x0B
0xE0040FECPID3RO0x00
0xE0040FF0CID0RO0x0DComponent identification registers
0xE0040FF4CID1RO0x90
0xE0040FF8CID2RO0x05
0xE0040FFCCID3RO0xB1

[a] IMPLEMENTATION DEFINED.


The following sections describe the TPIU registers whose implementation is specific to this processor. The Formatter, Integration Mode Control, and Claim Tag registers are described in the Arm® CoreSight™ Components Technical Reference Manual. Other registers are described in the Arm®v7-M Architecture Reference Manual.

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