3.2. Register summary

Table 3.1 shows the system control registers. Registers not described in this chapter are described in the Arm®v7-M Architecture Reference Manual.

Table 3.1. System control registers

0xE000E008ACTLRRW0x00000000Auxiliary Control Register
0xE000E010SYST_CSRRW0x00000000SysTick Control and Status Register
0xE000E014SYST_RVRRWUnknownSysTick Reload Value Register
0xE000E018SYST_CVRRWUnknownSysTick Current Value Register
0xE000E01CSYST_CALIBRO-[a]SysTick Calibration Value Register
0xE000ED00CPUIDRO0x411FC272CPUID Base Register
0xE000ED04ICSRRW or RO0x00000000Interrupt Control and State Register
0xE000ED08VTORRW-[b]Vector Table Offset Register
0xE000ED0CAIRCRRW0xFA050000[c]Application Interrupt and Reset Control Register
0xE000ED10SCRRW0x00000000System Control Register
0xE000ED14CCRRW[d]0x00040200Configuration and Control Register
0xE000ED18SHPR1RW0x00000000System Handler Priority Register 1
0xE000ED1CSHPR2RW0x00000000System Handler Priority Register 2
0xE000ED20SHPR3RW0x00000000System Handler Priority Register 3
0xE000ED24SHCSRRW0x00000000System Handler Control and State Register
0xE000ED28CFSRRW0x00000000Configurable Fault Status Registers[e]
0xE000ED2CHFSRRW0x00000000HardFault Status Register
0xE000ED30DFSRRW0x00000000Debug Fault Status Register
0xE000ED34MMFARRWUnknownMemManage Fault Address Register[f]
0xE000ED38BFARRWUnknownBusFault Address Register[f]
0xE000ED40ID_PFR0RO0x00000030Processor Feature Register 0
0xE000ED44ID_PFR1RO0x00000200Processor Feature Register 1
0xE000ED48ID_DFR0RO0x00100000Debug Feature Register 0[g]
0xE000ED4CID_AFR0RO0x00000000Auxiliary Feature Register 0
0xE000ED50ID_MMFR0RO0x00100030[h]Memory Model Feature Register 0
0xE000ED54ID_MMFR1RO0x00000000Memory Model Feature Register 1
0xE000ED58ID_MMFR2RO0x01000000Memory Model Feature Register 2
0xE000ED5CID_MMFR3RO0x00000000Memory Model Feature Register 3
0xE000ED60ID_ISAR0RO0x01101110Instruction Set Attributes Register 0
0xE000ED64ID_ISAR1RO0x02112000Instruction Set Attributes Register 1
0xE000ED68ID_ISAR2RO0x20232231Instruction Set Attributes Register 2
0xE000ED6CID_ISAR3RO0x01111131Instruction Set Attributes Register 3
0xE000ED70ID_ISAR4RO0x01310132Instruction Set Attributes Register 4
0xE000ED78CLIDRRO-[i]Cache Level ID Register
0xE000ED7CCTRRO0x8303C003Cache Type Register
0xE000ED80CCSIDRRO-[j]Cache Size ID Register
0xE000ED84CSSELRRWunpredictableCache Size Selection Register
0xE000ED88CPACRRW-Coprocessor Access Control Register
0xE000EF00STIRWO0x00000000Software Triggered Interrupt Register
0xE000EF50ICIALLUWOUnknownInstruction cache invalidate all to Point of Unification (PoU)
0xE000EF58ICIMVAUWOUnknownInstruction cache invalidate by address to PoU
0xE000EF5CDCIMVACWOUnknownData cache invalidate by address to Point of Coherency (PoC)
0xE000EF60DCISWWOUnknownData cache invalidate by set/way
0xE000EF64DCCMVAUWOUnknownData cache by address to PoU
0xE000EF68DCCMVACWOUnknownData cache clean by address to PoC
0xE000EF6CDCCSWWOUnknownData cache clean by set/way
0xE000EF70DCCIMVACWOUnknownData cache clean and invalidate by address to PoC
0xE000EF74DCCISWWOUnknownData cache clean and invalidate by set/way
0xE000EF78BPIALLRAZ/WIUnknownNot implemented
0xE000EF90CM7_ITCMCRRWUnknownInstruction and Data Tightly-Coupled Memory Control Registers
0xE000EF98CM7_AHBPCRRWUnknownAHBP Control Register
0xE000EF9CCM7_CACRRWUnknownL1 Cache Control Register
0xE000EFA0CM7_AHBSCRRWUnknownAHB Slave Control Register
0xE000EFA8CM7_ABFSRRWUnknownAuxiliary Bus Fault Status Register
0xE000EFB0IEBR0[k]RW-Instruction Error bank Register 0-1
0xE000EFB8DEBR0[k]RW-Data Error bank Register 0-1
0xE000EFD0PID4 -0x00000004

See the Component and Peripheral ID register formats in the Arm®v7-M Architecture Reference Manual.

0xE000EFD4PID5 -0x00000000
0xE000EFD8PID6 -0x00000000
0xE000EFDCPID7 -0x00000000
0xE000EFE0PID0 --[l]
0xE000EFE4PID1 -0x000000B0
0xE000EFF0CID0 -0x0000000D
0xE000EFF4CID1 -0x000000E0
0xE000EFF8CID2 -0x00000005
0xE000EFFCCID3 -0x000000B1

[a] SYST_CALIB indicates the value of signal CFGSTCALIB[25:0]. See Table 3.2.

[b] VTOR[31:7] indicates the value of signal INITVTOR[31:7]. VTOR[6:0] are RAZ.

[c] AIRCR[15] indicates the value of signal CFGBIGEND.

[d] The processor implements bit[9] of CCR, STKALIGN, as RO and has a value of 1.

[e] The 32-bit CFSR comprises the status registers for the faults that have configurable priority. Software can access the combined CFSR, or use byte or halfword accesses to access the individual registers, MemManage Status Register (MMFSR), BusFault Status Register (BFSR), and UsageFault Status Register (UFSR). See the Arm®v7-M Architecture Reference Manual for more information.

[f] BFAR and MFAR are the same physical register. Because of this, the BFARVALID and MFARVALID bits are mutually exclusive.

[g] ID_DFR0 reads as 0 if no debug support is implemented.

[h] The reset value depends on the values of signals CFGITCMSZ and CFGDTCMSZ.

[i] The reset value depends on whether L1 cache is implemented.

[j] Reset value depends on which caches are implemented and their sizes.

[k] Only present if ECC is present, otherwise RAZ/WI.

[l] This value is 0x00000000 for implementations without FPU or 0x0000000C for implementations with FPU.

Table 3.2 shows how signal CFGSTCALIB[25:0] is indicated in register SYST_CALIB.

Table 3.2. SYST_CALIB inputs

[29:24]-None. RAZ.

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