4.1.4. Disabling cache error checking and correction

If cache error checking and correction is included in the processor it is enabled by default from reset. The following code example can be used to disable the feature. The operation is carried out by modifying the CM7_CACR.ECCEN bit the PPB memory region.

CM7_CACR    EQU 0xE000EF9C

        LDR r11, =CM7_CACR
        LDR r0, [r11]
        BFC r0, #0x1, #0x1    ; Clear CM7_CACR.ECCEN
        STR r0, [r11]


Care must be taken when software changes the error checking fields in the CM7_CACR. If the fields are changed when the caches contain data, ECC information in the caches might not be correct for the new setting, resulting in unexpected errors and data loss. Therefore the fields in the CM7_CACR must only be changed when both caches are turned off and the entire cache must be invalidated after the change.

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F