5.5.1. AXI attributes and transactions

Table 5.3 shows the AXI attributes and transactions for the AXIM interface when the processor is configured with the L1 data cache. This is for use in a native AXI system with high memory bandwidth and supports multiple outstanding transactions, also known as a high performance AXIM interface.

Table 5.3. High performance AXIM attributes and transactions

AttributeValueDescription
Write issuing capability39

Consisting of:

  • 15 writes to Strongly-ordered or Device memory.

  • 24 writes to Normal memory, that can be evictions, write bursts or single writes. A maximum of 17 of these can be to cacheable memory and a maximum of 10 to Non-cacheable or shareable memory.

Read issuing capability7

Consisting of:

  • 2 data linefills.

  • 4 Non-cacheable data reads.

  • 1 instruction fetch or instruction linefill.

Write ID capability4

Consisting of:

  • 1 reserved for Strongly-ordered or Device memory.

  • 1 reserved for Normal, cacheable and Non-shareable memory.

  • 1 reserved for Normal, Non-cacheable or Shareable memory.

  • 1 reserved for cache line evictions (Normal, cacheable, Write-Back memory).

Read ID capability4-
Combined issuing capability40

Consisting of:

  • 39 outstanding writes.

  • 1 instruction fetch[a].

[a] The maximum issuing capability of the memory system is limited to one outstanding instruction read because all data reads are hazarded in the BIU when the maximum number of write transactions have been issued.


Only a subset of all possible AXI transactions can be generated. These are:

For more information on IDs used for different transactions, see Identifiers for AXIM interface accesses.

Table 5.4 shows the AXI attributes and transactions for when the processor is not configured to include the L1 data cache. That is, if you want to use it in a low-cost AXI system, or bridged to AHB, that has a low-bandwidth memory system, like on an off-chip memory system.

Table 5.4. Area optimized AXIM attributes and transactions

AttributeValueDescription
Write issuing capability25

Consisting of:

  • 15 writes to Strongly-ordered or Device memory.

  • 10 writes to Normal memory.

Read issuing capability5

Consisting of:

  • 4 data read.

  • 1 instruction fetch or instruction linefill.

Write ID capability2

Consisting of:

  • 1 reserved for Strongly-ordered or Device memory.

  • 1 reserved for Normal memory.

Read ID capability2-
Combined issuing capability26

Consisting of:

  • 25 outstanding writes.

  • 1 instruction fetch[a].

[a] The maximum issuing capability of the memory system is limited to one outstanding instruction read because all data reads are hazarded in the BIU when the maximum number of write transactions have been issued.


Only a subset of all possible AXI transactions can be generated. These are:

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