9.2. About the AHBD interface

The 32-bit AHB debug (AHBD) interface implements the AMBA 3 AHB-Lite protocol. It can be used with a CoreSight AHB-AP to provide debugger access to:

AHBD interface accesses are only in little-endian format. The processor ensures data is presented in the correct big- or little-endian format to the system. This is transparent to the debugger.


  • The instruction cache is not accessible to a debugger. Therefore debugger accesses to cacheable, executable regions of memory might not be coherent with the instructions visible to the instruction side of the processor.

  • The data cache must be enabled by setting the CCR.DC to 1 to read and write data to the cache. If CCR.DC is set to 0, all debug requests to memory regions outside the TCM and peripheral address space, access only the external memory on AXIM even if the debug request is marked as cacheable on the AHBD interface.

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F