13.1. About the Cortex-M7 TPIU

The Cortex-M7 TPIU is an optional component that bridges between the on-chip trace data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a data stream. The Cortex-M7 TPIU encapsulates IDs where required, and the data stream is then captured by an external Trace Port Analyzer (TPA).

The Cortex-M7 TPIU is a variant of the CoreSight SoC-400 TPIU that is specially designed for low-cost debug. Your implementation can replace the Cortex-M7 TPIU with other CoreSight components if your implementation requires the additional features of the CoreSight SoC-400 TPIU.

Note

The CM7TPIU only supports the ETM Instruction trace interface, configuration parameter ETM set to 1.

In this chapter, the term TPIU refers to the Cortex-M7 TPIU. For information about the CoreSight SoC-400 TPIU, see the Arm® CoreSight™ SoC-400 Technical Reference Manual.

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