4.1.3. Initializing and enabling the L1 cache

If the processor has been implemented with L1 data or instruction caches, they must be invalidated before they are enabled in software, otherwise unpredictable behavior can occur.

Invalidate the entire data cache

Software can use the following code example to invalidate the entire data cache, if it has been included in the processor. The operation is carried out by iterating over each line of the cache and using the DCISW register in the Private Peripheral Bus (PPB) memory region to invalidate the line. The number of cache ways and sets is determined by reading the CCSIDR register.

CCSIDR  EQU 0xE000ED80          ; Cache size ID register address
CSSELR  EQU 0xE000ED84          ; Cache size selection register address
DCISW   EQU 0xE000EF60          ; Cache maintenance op address: data cache clean and invalidate by set/way

                                ; CSSELR selects the cache visible in CCSIDR
MOV r0, #0x0                    ; 0 = select “level 1 data cache”
LDR r11, =CSSELR                ;
STR r0, [r11]                   ;
DSB                             ; Ensure write to CSSELR before proceeding

LDR r11, =CCSIDR                ; From CCSIDR
LDR r2, [r11]                   ; Read data cache size information
AND r1, r2, #0x7                ; r1 = cache line size
ADD r7, r1, #0x4                ; r7 = number of words in a cache line

UBFX r4, r2, #3, #10            ; r4 = number of “ways”-1 of data cache

UBFX r2, r2, #13, #15           ; r2 = number of “set”-1 of data cache

CLZ r6, r4                      ; calculate bit offset for “way” in DCISW

LDR r11, =DCISW                 ; invalidate cache by set/way

inv_loop1                       ; For each “set”
MOV r1, r4                      ;   r1 = number of “ways”-1
LSLS r8, r2, r7                 ;   shift “set” value to bit 5 of r8

inv_loop2                       ; For each “way”
LSLS r3, r1, r6                 ;   shift “way” value to bit 30 in r6
ORRS r3, r3, r8                 ;   merge “way” and “set” value for DCISW
STR r3, [r11]                   ;   invalidate D-cache line
SUBS r1, r1, #0x1               ;   decrement “way”
BGE inv_loop2                   ; End for each “way”

SUBS r2, r2, #0x1               ; Decrement “set”
BGE inv_loop1                   ; End for each “set”

DSB                             ; Data sync barrier after invalidate cache
ISB                             ; Instruction sync barrier after invalidate cache
Invalidate instruction cache

You can use the following code example to invalidate the entire instruction cache, if it has been included in the processor. The operation is carried out by writing to the ICIALLU register in the PPB memory region.

ICIALLU EQU 0xE000EF50

        MOV r0, #0x0
        LDR r11, =ICIALLU
        STR r0, [r11]

        DSB
        ISB
Enabling data and instruction caches

You can use the following code example to enable the data and instruction cache after they have been initialized. The operation is carried out by modifying the CCR.IC and CCR.DC fields in the PPB memory region.

CCR     EQU 0xE000ED14

        LDR r11, =CCR
        LDR r0, [r11]
        ORR r0, r0, #0x1:SHL:16    ; Set CCR.DC field
        ORR r0, r0, #0x1:SHL:17    ; Set CCR.IC field
        STR r0, [r11]

        DSB
        ISB
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