12.3. ITM programmers model

Table 12.1 shows the ITM registers whose implementation is specific to this processor. Other registers are described in the Arm®v7-M Architecture Reference Manual.

Depending on the implementation of your processor, the ITM registers might not be present. Any register that is configured as not present reads as zero.

Note

  • You must enable TRCENA of the Debug Exception and Monitor Control Register before you program or use the ITM.

  • If the ITM stream requires synchronization packets, you must configure the synchronization packet rate in the DWT.


Table 12.1. ITM register summary

AddressNameType

Reset

Description

0xE0000000-

0xE000007C

ITM_STIM0- ITM_STIM31RW-Stimulus Port Registers 0-31
0xE0000E00ITM_TERRW0x00000000Trace Enable Register
0xE0000E40ITM_TPRRW0x00000000ITM Trace Privilege Register
0xE0000E80ITM_TCRRW0x00000000Trace Control Register
0xE0000EF0ITM_ITATRDYROUnknownIntegration Mode: Read ATB Ready
0xE0000EF8ITM_ITATVALWO-Integration Mode: Write ATB Valid
0xE0000F00ITM_TCTRLRW0x00000000Integration Mode Control Register
0xE0000FB0ITM_LARWO-Lock Access Register
0xE0000FB4ITM_LSRROUnknownLock Status Register
0xE0000FD0PID4RO0x00000004Peripheral identification registers
0xE0000FD4PID5RO0x00000000
0xE0000FD8PID6RO0x00000000
0xE0000FDCPID7RO0x00000000
0xE0000FE0PID0RO0x00000001
0xE0000FE4PID1RO0x000000B0
0xE0000FE8PID2RO0x0000000B
0xE0000FECPID3RO0x00000000
0xE0000FF0CID0RO0x0000000DComponent identification registers
0xE0000FF4CID1RO0x000000E0
0xE0000FF8CID2RO0x00000005
0xE0000FFCCID3RO0x000000B1

Note

ITM registers are fully accessible in privileged mode. In user mode, all registers can be read, but only the Stimulus Registers and Trace Enable Registers can be written, and only when the corresponding Trace Privilege Register bit is set. Invalid user mode writes to the ITM registers are discarded.

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