9.3.2. FPB programmers model

Table 9.7 shows the FPB registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.


Table 9.7. FPB register summary

AddressNameTypeResetDescription
0xE0002000FP_CTRLRW

0x10000040[a]

0x10000080[b]

FlashPatch Control Register
0xE0002004FP_REMAPRAZ/WI-Not implemented
0xE0002008FP_COMP0RW0b00000000[c]FlashPatch Comparator Register0
0xE000200CFP_COMP1RW0b00000000FlashPatch Comparator Register1
0xE0002010FP_COMP2RW0b00000000FlashPatch Comparator Register2
0xE0002014FP_COMP3RW0b00000000FlashPatch Comparator Register3
0xE0002018FP_COMP4RW0b00000000FlashPatch Comparator Register4
0xE000201CFP_COMP5RW0b00000000FlashPatch Comparator Register5
0xE0002020FP_COMP6RW0b00000000FlashPatch Comparator Register6
0xE0002024FP_COMP7RW0b00000000FlashPatch Comparator Register7
0xE0002FB0FP_LARWO-FlashPatch Lock Access Register
0xE0002FB4FP_LSRROUnknownFlashPatch Lock Status Register
0xE0002FD0PID4RO0x00000004Peripheral identification registers
0xE0002FD4PID5RO0x00000000
0xE0002FD8PID6RO0x00000000
0xE0002FDCPID7RO0x00000000
0xE0002FE0PID0RO0x0000000E
0xE0002FE4PID1RO0x000000B0
0xE0002FE8PID2RO0x0000000B
0xE0002FECPID3RO0x00000000
0xE0002FF0CID0RO0x0000000DComponent identification registers
0xE0002FF4CID1RO0x000000E0
0xE0002FF8CID2RO0x00000005
0xE0002FFCCID3RO0x000000B1

[a] If four instruction comparators are implemented.

[b] If eight instruction comparators are implemented.

[c] For FP_COMP0 to FP_COMP7, bit 0 is reset to 0. Other bits in these registers are not reset.


All FPB registers are described in the Arm®v7-M Architecture Reference Manual.

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