11.3. DWT programmers model

Table 11.1 shows the DWT registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.


Table 11.1. DWT register summary

AddressNameType

Reset

Description
0xE0001000DWT_CTRLRW

See [a]

Control Register
0xE0001004DWT_CYCCNTRW0x00000000Cycle Count Register
0xE0001008DWT_CPICNTRW-CPI Count Register
0xE000100CDWT_EXCCNTRW-Exception Overhead Count Register
0xE0001010DWT_SLEEPCNTRW-Sleep Count Register
0xE0001014DWT_LSUCNTRW-LSU Count Register
0xE0001018DWT_FOLDCNTRW-Folded-instruction Count Register
0xE000101CDWT_PCSRRO-Program Counter Sample Register
0xE0001020DWT_COMP0RW-Comparator Register 0
0xE0001024DWT_MASK0RW-Mask Register 0
0xE0001028DWT_FUNCTION0RW0x00000000Function Register 0
0xE0001030DWT_COMP1RW-Comparator Register 1
0xE0001034DWT_MASK1RW-Mask Register1
0xE0001038DWT_FUNCTION1RW0x00000000[b]Function Register 1
0xE0001040DWT_COMP2RW-Comparator Register 2
0xE0001044DWT_MASK2RW-Mask Register 2
0xE0001048DWT_FUNCTION2RW0x00000000Function Register 2
0xE0001050DWT_COMP3RW-Comparator Register 3
0xE0001054 DWT_MASK3RW-Mask Register 3
0xE0001058 DWT_FUNCTION3RW0x00000000Function Register 3
0xE0001FB0DWT_LARWO-Lock Access Register
0xE0001FB4DWT_LSRROUnknownLock Status Register
0xE0001FD0PID4RO0x00000004Peripheral identification registers
0xE0001FD4PID5RO0x00000000
0xE0001FD8PID6RO0x00000000
0xE0001FDCPID7RO0x00000000
0xE0001FE0PID0RO0x00000002
0xE0001FE4PID1RO0x000000B0
0xE0001FE8PID2RO0x0000000B
0xE0001FECPID3RO0x00000000
0xE0001FF0CID0RO0x0000000DComponent identification registers
0xE0001FF4CID1RO0x000000E0
0xE0001FF8CID2RO0x00000005
0xE0001FFCCID3RO0x000000B1

[a] Possible reset values are:

  • 0x40000000 for full DWT, with trace.

  • 0x48000000 for full DWT, without trace.

  • 0x20000000 for reduced DWT, with trace.

  • 0x28000000 for reduced DWT, without trace.

[b] If the processor is configured for minimal debug, the DWT_FUNCTION1[9] is always RAZ.

If the processor is configured for full debug, the DWT_FUNCTION1[9] is always RA0.

All other bits in the DWT_FUNCTION1 register are reset to zero.


DWT registers are described in the Arm®v7-M Architecture Reference Manual.

Note

  • Cycle matching functionality is only available in comparator 0.

  • Data matching functionality is only available in comparator 1.

  • Data value is only sampled for accesses that do not produce an MPU or bus fault. The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst.

  • The FUNCTION field in the DWT_FUNCTION1 register is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches.

  • Arm does not recommend PC match for watchpoints because watchpoints are asynchronous to the event that causes them. It mainly guards and triggers the ETM.

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