9.1.4. Debug register summary

Table 9.6 shows the debug registers. Each of these registers is 32 bits wide and is described in the Arm®v7-M Architecture Reference Manual.

Table 9.6. Debug registers

AddressNameTypeResetDescription
0xE000ED30DFSRRW0x00000000[a]Debug Fault Status Register
0xE000EDF0DHCSRRW0x00000000Debug Halting Control and Status Register
0xE000EDF4DCRSRWO-Debug Core Register Selector Register
0xE000EDF8DCRDRRW-Debug Core Register Data Register
0xE000EDFCDEMCRRW0x00000000Debug Exception and Monitor Control Register

[a] Power-on reset only.


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