9.1.3. System Control Space

The processor provides debug through registers in the SCS. See:

SCS CoreSight identification

Table 9.5 shows the SCS CoreSight identification registers and values for debugger detection. Final debugger identification of the Cortex-M7 processor is through the CPUID register in the SCS. See CPUID Base Register.

Table 9.5. SCS identification values

0xE000EFD0 Peripheral ID40x00000004Component and Peripheral ID register formats in the Arm®v7-M Architecture Reference Manual
0xE000EFD4Peripheral ID50x00000000
0xE000EFD8Peripheral ID60x00000000
0xE000EFDCPeripheral ID70x00000000
0xE000EFE0Peripheral ID00x0000000C[a]
0xE000EFE4Peripheral ID10x000000B0
0xE000EFE8Peripheral ID20x0000000B
0xE000EFECPeripheral ID30x00000000
0xE000EFF0Component ID00x0000000D
0xE000EFF4Component ID10x000000E0
0xE000EFF8Component ID20x00000005
0xE000EFFCComponent ID30x000000B1

[a] 0x0000000C SCS identification value for implementations without FPU.

See the Arm®v7-M Architecture Reference Manual and the Arm® CoreSight™ Architecture Specification (v2.0) for more information about the ROM table ID and component registers, and their addresses and access types.

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