9.1.2. Cortex-M7 PPB ROM table identification and entries

Table 9.3 shows the Cortex-M7 PPB ROM table identification registers and values for debugger detection. This permits debuggers to identify the CoreSight components on the PPB in the processor and their debug capabilities.

Table 9.3. Cortex-M7 PPB ROM table identification values

AddressRegisterValueDescription
0xE00FFFD0Peripheral ID40x00000004

Component and Peripheral ID register formats in the Arm®v7-M Architecture Reference Manual

0xE00FFFD4Peripheral ID50x00000000
0xE00FFFD8Peripheral ID60x00000000
0xE00FFFDCPeripheral ID70x00000000
0xE00FFFE0Peripheral ID00x000000C7
0xE00FFFE4Peripheral ID10x000000B4
0xE00FFFE8Peripheral ID20x0000000B
0xE00FFFECPeripheral ID30x00000000
0xE00FFFF0Component ID00x0000000D
0xE00FFFF4Component ID10x00000010
0xE00FFFF8Component ID20x00000005
0xE00FFFFCComponent ID30x000000B1

These values for the Peripheral ID registers identify this as the Cortex-M7 PPB ROM table. The Component ID registers identify this as a CoreSight ROM table.

Note

The Cortex-M7 PPB ROM table only supports word size transactions.

Table 9.4 shows the CoreSight components that the Cortex-M7 PPB ROM table points to. The values depend on the implemented debug configuration.

Table 9.4. Cortex-M7 PPB ROM table components

AddressComponentValueDescription
0xE00FF000SCS0xFFF0F003See System Control Space.
0xE00FF004DWT0xFFF02003See Table 11.1.
0xE00FF008FPB0xFFF03003See Table 9.7.
0xE00FF00CITM0xFFF01003[a]See Table 12.1.
0xE00FF010Reserved (TPIU)0xFFF41002 Not present, TPIU not implemented inside Cortex-M7.
0xE00FF014Reserved (ETM)0xFFF42002Not present, ETM is referenced by the Cortex-M7 Processor ROM table. See Cortex-M7 Processor ROM table identification and entries.
0xE00FF018End marker0x00000000See DAP accessible ROM table in the Arm®v7-M Architecture Reference Manual.
0xE00FFFCCSYSTEM ACCESS0x00000001

[a] Reads as 0xFFF01002 if the ITM is not implemented.


The Cortex-M7 PPB ROM table entries point to the debug components of the processor. The offset for each entry is the offset of that component from the ROM table base address, 0xE00FF000.

See the Arm®v7-M Architecture Reference Manual and the Arm® CoreSight™ Architecture Specification (v2.0) for more information about the ROM table ID and component registers, and their addresses and access types.

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