8.2. FPU functional description

This section describes the operations and that the FPU supports and what exceptions the FPU generates.

The FPU fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.

The FPU provides an extension register file containing 32 single-precision registers. These can be viewed as:

For more information about the FPU, see the Arm®v7-M Architecture Reference Manual.

This section contains the following:

The modes of operation are controlled using the Floating-Point Status and Control Register, FPSCR. For more information about the FPSCR see the ARMv7-M Architecture Reference Manual.

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