2.4. System address map

The processor contains an internal bus matrix that arbitrates the processor and external AHBD memory accesses to both the external memory system and to the internal SCS and debug components.

Priority is always given to the processor to ensure that any debug accesses are as non-intrusive as possible.

Figure 2.1 shows the system address map.

Figure 2.1. System address map

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 2.1 shows the processor interfaces that are addressed by the different memory map regions.

Table 2.1. Memory regions

Memory MapRegion
CodeInstruction fetches and data accesses are performed over the ITCM or AXIM interface. When implemented and enabled, the ITCM is located at address 0x00000000.
SRAMInstruction fetches and data accesses are performed over the DTCM or AXIM interface. When implemented and enabled, the DTCM is located at address 0x20000000.
Peripheral

Data accesses are performed over the AHBP or AXIM interface.

When implemented and enabled, the AHBP is located at address 0x40000000.

Instruction fetches are performed over the AXIM interface.

External RAMInstruction fetches and data accesses are performed over the AXIM interface.
External DeviceInstruction fetches and data accesses are performed over the AXIM interface.
Private Peripheral Bus

Data accesses to registers associated with peripherals outside the processor are performed on the External Private Peripheral Bus (EPPB) interface. See Private peripheral bus.

This memory region is Execute Never (XN), and so instruction fetches are prohibited. An MPU, if present, cannot change this.

SystemSystem segment for vendor system peripherals. Data accesses are performed over the AHBP interface. This memory region is XN, and so instruction fetches are prohibited. An MPU, if present, cannot change this.

See the Arm®v7-M Architecture Reference Manual for more information about the memory model.

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F
Non-ConfidentialID121118