2.7. Exceptions

The processor and the NVIC prioritize and handle all exceptions. When handling exceptions:

The processor supports tail-chaining that enables back-to-back interrupts without the overhead of state saving and restoration.

You configure the number of interrupts, and levels of interrupt priority, during implementation. Software can choose only to enable a subset of the configured number of interrupts, and can choose how many levels of the configured priorities to use.

Note

The EPSR.T bit supports the Arm architecture interworking model, however, as ARMv7-M only supports execution of Thumb instructions, it must always be maintained with the value 1. This means that all exception vectors must have bit[0] set. If bit[0] of the associated vector table entry is set to 0 on exception entry, execution of the first instruction causes an INVSTATE UsageFault. If this happens on a reset, this escalates to a HardFault, because UsageFault is disabled on reset.

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