14.2.4. RAM configuration

Table 14.2 shows the RAM configuration with or without ECC when the processor is implemented with 4KB instruction and data cache.

Table 14.2. RAM configuration with or without ECC

RAMStorage for a RAM set without ECCStorage for a RAM set with ECC
Data tag RAM4x26 bits4x(26+7) bits
Data data RAM8x32 bits8x(32+7) bits
Instruction tag RAM4x22 bits4x(22+7) bits
Instruction data RAM4x64 bits4x(64+8) bits

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