3.3.8. L1 Cache Control Register

The CM7_CACR characteristics are:


Controls the L1 ECC and the L1 cache coherency usage model.

Usage Constraints

Accessible in privileged mode only.


Available in all configurations.


See the register summary in Table 3.1.

Figure 3.8 shows the CM7_CACR bit assignments.

Figure 3.8. CM7_CACR bit assignments

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Table 3.11 shows the CM7_CACR bit assignments.

Table 3.11. CM7_CACR bit assignments

[31:3]--Reserved, RAZ/WI.

Enables Force Write-Through in the data cache:


Disables Force Write-Through.


Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through.

This bit is RAZ/WI if the data cache is excluded. If the data cache is included the reset value of FORCEWT is 0.


Enables ECC in the instruction and data cache:


Enables ECC in the instruction and data cache. This is RAO/WI if both data cache and instruction cache are excluded or if ECC is excluded.


Disables ECC in the instruction and data cache.


Shared cacheable-is-WT for data cache. Enables limited cache coherency usage:


Normal Cacheable Shared locations are treated as being Non-cacheable. Programmed inner cacheability attributes are ignored. This is the default mode of operation for Shared memory. The data cache is transparent to software for these locations and therefore no software maintenance is required to maintain coherency.


Normal Cacheable shared locations are treated as Write-Through. Programmed inner cacheability attributes are ignored. All writes are globally visible. Other memory agent updates are not visible to Cortex-M7 processor software without suitable cache maintenance.

Useful for heterogeneous MP-systems where, for example, the Cortex-M7 processor is integrated on the Accelerator Coherency Port (ACP) interface on an MP-capable processor.

This bit is RAZ/WI when data cache is not configured.

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