6.3. MPU programmers model

Table 6.1 shows the MPU registers. These registers are described in the Arm®v7-M Architecture Reference Manual.

Table 6.1. MPU registers

AddressNameType

Reset

Description
0xE000ED90MPU_TYPERO

0x00000800[a]

MPU Type Register
0xE000ED94MPU_CTRLRW0x00000000MPU Control Register
0xE000ED98MPU_RNRRW

Unknown

MPU Region Number Register
0xE000ED9CMPU_RBARRW

Unknown

MPU Region Base Address Register
0xE000EDA0MPU_RASRRW

Unknown

MPU Region Attribute and Size Register
0xE000EDA4MPU_RBAR_A1RW

Unknown

MPU alias registers
0xE000EDA8MPU_RASR_A1RW

Unknown

0xE000EDACMPU_RBAR_A2RW

Unknown

0xE000EDB0MPU_RASR_A2RW

Unknown

0xE000EDB4MPU_RBAR_A3RW

Unknown

0xE000EDB8MPU_RASR_A3RW

Unknown

[a] The reset value depends on the number of regions implemented:

0x00000000

0 regions.

0x00000800

8 regions.

0x00001000

16 regions.


Note

The MPU registers support aligned word accesses only. Byte and halfword accesses are unpredictable.

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