1.7. Product revisions

This section describes the differences in functionality between product revisions:

r0p0

First release.

r0p1

The following changes have been made in this release:

  • Updated CPUID reset value, 0x410FC271.

  • Various engineering errata fixes.

r0p2

The following changes have been made in this release:

  • Updated CPUID reset value, 0x410FC272.

  • Various engineering errata fixes.

r1p0

The following changes have been made in this release:

  • Updated CPUID reset value, 0x411FC270.

  • Added CTLPPBLOCK[3:0] to allow locking of registers ITCMCR, DTCMCR, AHBPCR, VTOR to prevent unwanted updates.

  • Added ACTLR bit functions to allow low-capability AXI systems to disable AXI reads to DEV/SO memory and disable exclusive reads/writes to shared memory not initiated until all outstanding reads/stores on AXI are complete.

  • Added MBISTIMPERR[2] output to MBIST interface to provide an error when attempting to access unimplemented memory.

  • Improved handling of simultaneous AHBS and software activity relating to the same TCM.

r1p2

The following changes have been made in this release:

  • Updated CPUID reset value, 0x411FC272.

  • Added section describing speculative accesses, which are used by the processor to increase performance.

  • Updated section describing AXI transactions generated for Strongly-ordered or Device memory.

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