5.3.1. Faults

The classes of fault that can occur are:

MPU faults

The MPU can generate a fault for various reasons. MPU faults are always synchronous, and take priority over external faults. If an MPU fault occurs on an access that is not in the TCM, the AXI or AHB transactions for that access are not performed.

External faults

A memory access or instruction fetch performed through the AXIM interface can generate two different types of error response, a slave error (SLVERR) or decode error (DECERR). These are known as external AXI errors, because they are generated by the AXI system outside the processor.

A memory access performed through the AHBP interface can generate a single error response. The processor manages this in the same way as a response of SLVERR from the AXI interface.

A memory or instruction fetch access performed on the TCM interface can generate a single error response. The processor manages this in the same way as a response of SLVERR from the AXI interface.

Synchronous faults are generated for instruction fetches and data loads. All stores generate asynchronous faults.

Note

An AXI slave device in the system that cannot handle exclusive transactions returns OKAY in response to an exclusive read. This is also treated as an external error, and the processor behaves as if the response was SLVERR.

Debug events

The debug logic in the processor can be configured to generate breakpoints or vector capture events on instruction fetches, and watchpoints on data accesses. If the processor is software-configured for monitor-mode debugging, a fault is taken when one of these events occurs, or when a BKPT instruction is executed. For more information, see Chapter 9 Debug.

Synchronous and asynchronous faults

See External faults for more information about the differences between synchronous and asynchronous faults.

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