5.6.1. AHBP interface transfers

The AHBP interface conforms to the AHB-Lite specification, but it does not generate all the AHB transaction types that the specification permits. This section describes the types of AHB transaction that the AHBP interface does not generate. If you are designing an AHB slave to work only with the Cortex-M7 processor AHBP interface, you can take advantage of these restrictions and the interface attributes described in the following sections to simplify the slave.

This section also contains tables that show some of the types of AHB transaction that the processor generates. However, because a particular type of transaction is not shown here does not mean that the processor does not generate such a transaction.

Note

An AHB slave device connected to the AHBP interface must be capable of handling every kind of transaction permitted by the AHB specification, except where there is an explicit statement in this chapter that such a transaction is not generated. You must not infer any additional restrictions from the example tables given.

Restrictions on AHBP interface transfers describes restrictions on the type of transfers that the AHBP interface generates.

The following sections give examples of transfers generated by the AHBP interface:

Restrictions on AHBP interface transfers

The AHBP interface applies the following restrictions to the AHB transactions it generates:

  • The interface only uses one transfer and all bursts are single, that is HBURSTP[2:0] is always SINGLE.

  • No transaction ever crosses a 4-byte boundary in memory.

  • The transfer type, that is, HTRANSP[2:0] is never BUSY or SEQUENTIAL.

  • The transfer size is never greater than 32 bits because it is a 32-bit AHB bus.

  • All transactions are data accesses, that is HPROTP[0] is always 1.

  • Transactions to Device and Strongly-ordered memory are always to addresses that are aligned for the transfer size.

  • Exclusive accesses are always to addresses that are aligned for the transfer size.

Strongly-ordered and Device transactions

A load or store instruction, to or from Strongly-ordered or Device memory, always generates AHB transactions of the size implied by the instruction. All accesses using LDM, STM, LDRD, or STRD instructions to Strongly-ordered or Device memory occur as single 32-bit transfers.

LDRB

Table 5.24 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an LDRB from bytes 0-3 in Strongly-ordered or Device memory.

Table 5.24. LDRB transfers

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (byte 0)0x00Single8-bit
0x1 (byte 1)0x01Single8-bit
0x2 (byte 2)0x02Single8-bit
0x3 (byte 3)0x03Single8-bit

LDRH

Table 5.25 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an LDRH from halfwords 0-1 in Strongly-ordered or Device memory.

Table 5.25. LDRH transfers

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (halfword 0)0x00Single16-bit
0x2 (halfword 1)0x02Single16-bit

Note

A load of a halfword from Strongly-ordered or Device memory addresses 0x1 or 0x3 generates an alignment UsageFault.

LDR or LDM of one register

Table 5.26 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an LDR or an LDM that transfers one register, an LDM1, in Strongly-ordered or Device memory.

Table 5.26. LDR or LDM of one register

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (word 0)0x00Single32-bit

Note

A load of a word from Strongly-ordered or Device memory addresses 0x1, 0x02, 0x3, 0x5, 0x06, or 0x7 generates an alignment UsageFault.

LDM that transfers five registers

Table 5.27 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an LDM that transfers five registers, an LDM5, in Strongly-ordered or Device memory.

Table 5.27. LDM that transfers five registers

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (word 0)

0x00

Single 32-bit

0x04

Single 32-bit

0x08

Single32-bit

0x0C

Single 32-bit
0x10Single32-bit
0x4 (word 1)0x04Single32-bit

0x08

Single32-bit

0x0C

Single 32-bit

0x10

Single32-bit

0x14

Single 32-bit

Note

A load of a word from Strongly-ordered or Device memory addresses 0x1, 0x2, or 0x3 generates an alignment UsageFault.

STRB

Table 5.28 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an STRB from bytes 0-3 in Strongly-ordered or Device memory.

Table 5.28. STRB transfers

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (byte 0)0x00Single8-bit
0x1 (byte 1)0x01Single8-bit
0x2 (byte 2)0x02Single8-bit
0x3 (byte 3)0x03Single8-bit

STRH

Table 5.29 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an STRH from halfwords 0-1 in Strongly-ordered or Device memory.

Table 5.29. STRH transfers

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (halfword 0)0x00Single16-bit
0x2 (halfword 1)0x02Single16-bit

Note

A store of a halfword to Strongly-ordered or Device memory addresses 0x1 or 0x3 generates an alignment UsageFault.

STR of one register

Table 5.30 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an STR that transfers one register in Strongly-ordered or Device memory.

Table 5.30. STR of one register

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (word 0)0x00Single32-bit

Note

A store of a word to Strongly-ordered or Device memory addresses 0x1, 0x2, or 0x3 generates an alignment UsageFault.

STM of five registers

Table 5.31 shows the values of HADDRP[1:0], HBURSTP, and HSIZEP for an STM that transfers five registers, an STM5, over the AHBP interface to Strongly-ordered or Device memory.

Table 5.31. STM of five registers

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (word 0)

0x00

Single32-bit

0x04

Single32-bit

0x08

Single32-bit

0x0C

Single32-bit
0x10Single32-bit
0x4 (word 1)0x04Single32-bit

0x08

Single32-bit

0x0C

Single32-bit

0x10

Single32-bit

0x14

Single32-bit

Note

A store of a word from Strongly-ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment UsageFault.

Normal reads

Load instructions accessing Normal memory generate AHBP interface transactions that might not be the same size or length as the instruction implies. The tables in this section give examples of AHBP transactions that might result from various load instructions, accessing various addresses in Normal memory. They are examples only, and are not an exhaustive description of the AHBP transactions.

LDRH

Table 5.32 shows possible values of HADDRP[2:0], HBURSTP, and HSIZEP for an LDRH from bytes 0 to 3 in Normal memory.

Table 5.32. LDRH transfers in Normal memory

Address[1:0]HADDRP[2:0]HBURSTPHSIZEP
0x0 (byte 0)0x00Single16-bit
0x1 (byte 1)0x00Single32-bit
0x2 (byte 2)0x02Single16-bit
0x3 (byte 3)[a]0x00Single32-bit
0x04Single32-bit

[a] AHBP interface transactions do not cross a double word boundary.


LDR

Table 5.33 shows possible values of HADDRP[2:0], HBURSTP, and HSIZEP for an LDR from Normal memory.

Table 5.33. LDR transfers in Normal memory

Address[1:0]HADDRP[2:0]HBURSTPHSIZEP
0x0 (byte 0)0x0Single32-bit
0x1 (byte 1)0x0Single32-bit
0x4Single32-bit
0x2 (byte 2)0x0Single32-bit
0x4Single32-bit
0x3 (byte 3)0x0Single32-bit
0x4Single32-bit

Normal writes

Store instructions accessing Normal memory generate AHBP interface transactions that might not be the same size or length as the instruction implies. The tables in this section give examples of AHBP transactions that might result from various store instructions, accessing various addresses in Normal memory. They are examples only, and are not an exhaustive description of the AHBP transactions.

STRH

Table 5.34 shows possible values of HADDRP[1:0], HBURSTP, and HSIZEP for an STRH from bytes 0 to 3 in Normal memory.

Table 5.34. STRH transfers in Normal memory

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (byte 0)0x00Single16-bit
0x1 (byte 1)0x01Single8-bit
0x02Single8-bit
0x2 (byte 2)0x02Single16-bit
0x3 (byte 3)0x03Single8-bit
0x04Single8-bit

STR or STM of one register

Table 5.35 shows possible values of HADDRP[1:0], HBURSTP, and HSIZEP for an STR to Normal memory.

Table 5.35. STR transfers in Normal memory

Address[1:0]HADDRP[1:0]HBURSTPHSIZEP
0x0 (byte 0, word 0)0x00Single32-bit
0x1 (byte 1)0x01Single8-bit
0x02Single16-bit
0x04Single8-bit
0x2 (byte 2)0x02Single16-bit
0x04Single16-bit
0x3 (byte 3)0x03Single8-bit
0x04Single16-bit
0x06Single8-bit

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F
Non-ConfidentialID121118