9.1.1. Cortex-M7 Processor ROM table identification and entries

Table 9.1 shows the processor ROM table identification registers and values for debugger detection. This permits debuggers to identify the processor.

Table 9.1. Cortex-M7 Processor ROM table identification values

0xE00FEFD0Peripheral ID40x00000004

Component and Peripheral ID register formats in the Arm®v7-M Architecture Reference Manual

0xE00FEFD4Peripheral ID50x00000000
0xE00FEFD8Peripheral ID60x00000000
0xE00FEFDCPeripheral ID70x00000000
0xE00FEFE0Peripheral ID00x000000C8
0xE00FEFE4Peripheral ID10x000000B4
0xE00FEFE8Peripheral ID20x0000000B
0xE00FEFECPeripheral ID30x00000000
0xE00FEFF0Component ID00x0000000D
0xE00FEFF4Component ID10x00000010
0xE00FEFF8Component ID20x00000005
0xE00FEFFCComponent ID30x000000B1

These values for the Peripheral ID registers identify this as the Cortex-M7 Processor ROM table. The Component ID registers identify this as a CoreSight ROM table.


The Cortex-M7 Processor ROM table only supports word-size transactions.

Table 9.2 shows the CoreSight components that the Cortex-M7 Processor ROM table points to.

Table 9.2. Cortex-M7 Processor ROM table components

0xE00FE000Cortex-M7 PPB ROM Table0x00001003See Cortex-M7 PPB ROM table identification and entries
0xE00FE004ETM0xFFF43003[a]See the Arm® CoreSight™ ETM-M7 Technical Reference Manual
0xE00FE008CTI0xFFF44003[b]See Chapter 10 Cross Trigger Interface
0xE00FE00CReserved0x1FF02002See the Arm® CoreSight™ Architecture Specification (v2.0)
0xE00FE010End marker0x00000000

[a] Reads as 0xFFF43002 if the ETM is not implemented.

[b] Reads as 0xFFF44002 if the CTI is not implemented.

The Cortex-M7 Processor ROM table entries point to the debug components of the processor. The offset for each entry is the offset of that component from the ROM table base address, 0xE00FE000.

See the Arm® CoreSight™ Architecture Specification (v2.0) for more information about the ROM table ID and component registers, and access types.

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