9.1. About debug

Cortex-M7 debug functionality includes processor halt, single-step, processor core register access, Vector Catch, unlimited software breakpoints, and full system memory access. See the Arm®v7-M Architecture Reference Manual for more information. The processor also includes support for hardware breakpoints and watchpoints configured during implementation:

For processors that implement debug, Arm recommends that a debugger identify and connect to the debug components using the CoreSight debug infrastructure.

Figure 9.1 shows the recommended flow that a debugger can follow to discover the components in the CoreSight debug infrastructure. In this case a debugger reads the peripheral and component ID registers for each CoreSight component in the CoreSight system.

Figure 9.1. CoreSight discovery

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To identify the Cortex-M7 processor within the CoreSight system, Arm recommends that a debugger perform the following actions:

  1. Locate and identify the Cortex-M7 Processor ROM table using its CoreSight identification. See Table 9.2 for more information.

  2. Follow the pointer in the Cortex-M7 Processor ROM table to the Cortex-M7 PPB ROM table. From the PPB ROM table pointers the following components can be identified:

    1. System Control Space (SCS).

    2. Breakpoint unit (FPB).

    3. Data Watchpoint and Trace unit (DWT).

    4. Instrumentation Trace Macrocell unit (IMT).

    See Table 9.4 for more information.

When a debugger identifies the SCS from its CoreSight identification, it can identify the processor and its revision number from the CPUID register in the SCS at address 0xE000ED00.

A debugger cannot rely on the Cortex-M7 Processor ROM table being the first ROM table encountered. One or more system ROM tables are required between the access port and the processor ROM table if other CoreSight components are in the system. If a system ROM table is present, this can include a unique identifier for the implementation.

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