1.1.3. Configuration options

The Cortex-M7 processor has configurable options that you can configure during the implementation and integration stages to match your functional requirements.

Table 1.1 shows the configurable options at build time of the processor.

Table 1.1. Implementation options

FeatureOptionsDone at
Floating-pointNo floating-point.Implementation
Single-precision floating-point only.
Single-precision and double-precision floating-point.
Instruction TCMNo instruction TCM.Integration
4KB-16MB (powers of 2).
Data TCMNo data TCM.Integration
4KB-16MB (powers of 2). The Data TCM is split equally into two TCMs, D0TCM, and D1TCM.
Instruction cache No instruction cache unit (ICU)[a].Implementation
Instruction cache unit is included.
Data cache Area optimized AXIM interface, no data cache unit (DCU)[b].Implementation
Performance optimized AXIM interface, data cache unit is included.
Instruction cache size4KB, 8KB, 16KB, 32KB, 64KB.Integration
Data cache size4KB, 8KB, 16KB, 32KB, 64KB.Integration
AHB peripheral size64MB, 128MB, 256MB, 512MB.Integration
ECC support on cachesNo ECC on instruction cache or data cache.Implementation
ECC on all implemented caches.
Protected memory regions0 region, 8 regions, 16 regions.Implementation
Interrupts1-240 interrupts.Implementation
Number bits of interrupt priorityBetween three and eight bits of interrupt priority, between 8 and 256 levels of priority.Implementation
Debug watchpoints and breakpointsReduced set. Two data watchpoints comparators and four breakpoint comparators.Implementation
Full set. Four data watchpoints comparators and eight breakpoint comparators.
ITM and Data Watchpoint and Trace (DWT) trace functionalityNo ITM or DWT trace.Implementation
Complete ITM and DWT trace.
ETMNo ETM support.Implementation
ETM instruction trace only.
ETM instruction and data trace.
Dual-redundant processorNo dual-redundant processor.Implementation
Dual-redundant processor included.
Reset All RegistersOnly required registers that must be initialized are reset in the RTL.Implementation
All registers are reset in the RTL excluding those in the ETM, if included.
All registers are reset in the RTL including those in the ETM, if included.
Cross Trigger Interface (CTI)No Cross Trigger Interface.Implementation
Cross Trigger Interface included.
Wake-up Interrupt Controller (WIC)No Wake-up Interrupt controller.Implementation
Wake-up Interrupt controller included.

[a] The ICU includes an instruction cache controller.

[b] The DCU includes a data cache controller.


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