3.3.1. Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Provides implementation defined configuration and control options for the processor.

Usage Constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1.

Figure 3.1 shows the ACTLR bit assignments.

Figure 3.1. ACTLR bit assignments

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Table 3.3 shows the ACTLR bit assignments.

Table 3.3. ACTLR bit assignments

BitsNameFunction
[31:29]-Reserved.
[28]DISFPUISSOPT
0

Normal operation.

[27]DISCRITAXIRUW

Disable critical AXI read-under-write:

0

Normal operation. This is backwards compatible with r0.

1

AXI reads to DEV/SO memory. Exclusive reads to shared memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete.

[26]DISDYNADD

Disables dynamic allocation of ADD and SUB instructions:

0

Normal operation. Some ADD and SUB instructions are resolved in EX1.

1

All ADD and SUB instructions are resolved in EX2.

[25:21]DISISSCH1
0

Normal operation.

1

Instruction type must not be issued in channel 1.

Bit [25]

VFP.

Bit [24]

Integer MAC and MUL.

Bit [23]

Loads to PC.

Bit [22]

Indirect branches, but not loads to PC.

Bit [21]

Direct branches.

[20:16]DISDI
0

Normal operation.

1

Nothing can be dual-issued when this instruction type is in channel 0.

Bit [20]

VFP.

Bit [19]

Integer MAC and MUL.

Bit [18]

Loads to PC.

Bit [17]

Indirect branches, but not loads to PC.

Bit [16]

Direct branches.

[15]DISCRITAXIRUR

Disables critical AXI Read-Under-Read.

0

Normal operation.

1

An AXI read to Strongly-ordered or Device memory, or an LDREX to shared memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set.

[14]DISBTACALLOC
0

Normal operation.

1

No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated.

[13]DISBTACREAD
0

Normal operation.

1

BTAC is not used and only static branch prediction can occur.

[12]DISITMATBFLUSH

Disables ITM and DWT ATB flush:

1

ITM and DWT ATB flush disabled. AFVALID is ignored and AFREADY is held HIGH.

Note

This bit is always 1 and therefore RAO/WI.

[11]DISRAMODE

Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions:

0

Normal operation.

1

Dynamic disabled.

[10]FPEXCODIS

Disables FPU exception outputs.

0

Normal operation.

1

FPU exception outputs are disabled.

[9:3]-Reserved.
[2]DISFOLD
0

Normal operation.

[1:0]-Reserved.

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