2.7.1. Exception handling

External read faults from either the TCM interfaces, the AXIM interface, or the AHB interfaces generate a synchronous exception in the processor. External write faults generate an asynchronous exception in the processor.

The processor implements advanced exception and interrupt handling, as described in the Arm®v7-M Architecture Reference Manual.

The processor exception model has the following implementation-defined behavior in addition to the architecturally-defined behavior:

To minimize interrupt latency, the processor can abandon the majority of multicycle instructions that are executing when an interrupt is recognized. The only exception is a load from Device or Strongly-ordered memory, or a shared store exclusive operation that starts on the AXI interface. All normal memory transactions are abandoned when an interrupt is recognized.

The processor restarts any abandoned operation on return from the interrupt. The processor also implements the Interruptible-continuable bits allowing load and store multiples to be interruptible and continuable. In these cases the processor resumes execution of these instructions after the last completed transfer instead of from the start. For more information on the Interruptible-continuable bits and key limitations on when they apply, see the Arm®v7-M Architecture Reference Manual.

Specifically, on the Cortex-M7 processor, these instructions always restart instead of continue:

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