5.7.3. AHBS interface arbitration

There are two relevant points of arbitration in the processor:

The processor supports five software-configurable arbitration modes:

When active, the round-robin AHBS arbitration scheme has the following characteristics:

The fairness counter determines which requestor gets access, where there is contention. This counter is decremented for each access where contention occurs, and is initialized to the CM7_AHBSCR.INITCOUNT field value when it reaches 0. See AHB Slave Control Register for more information about how to use CM7_AHBSCR.INITCOUNT.

Some limited software configurability is provided to moderate AHBS interface bandwidth by demoting its priority to a significantly lower level without shutting it out completely. This is achieved by increasing the initialization value of the fairness counter that forces arbitration of an AHBS interface access. It is also possible to invert the priority scheme to allow AHBS interface accesses to take priority over software accesses using the fairness counter.

Typically this AHBS interface bandwidth moderation feature is expected to be used for real-time critical code that runs in a high priority ISR. To allow individual ISRs to demote AHBS interface traffic, a threshold execution priority (TPRI) mode is provided to enable the processor hardware to automatically do this. See AHB Slave Control Register for more information about how to use TPRI.


The processor could stop executing code if the counter initialization value is 0 and the AHBS interface fully occupies the bandwidth of a TCM or the SQ.

The system can control the AHBS interface access priority directly using the AHBSPRI input signal on the processor. See AHB Slave Control Register.


  • Improper programming might directly degrade overall system performance.

  • For the AHBS interface to accept AHBS transactions all resets must be de-asserted.

  • Changes to CM7_AHBSCR might not occur immediately because the processor must completed existing AHBS interface traffic.

  • CM7_AHBSCR settings can be overruled and only be considered as a hint to the processor.

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F